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a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 revision: v1.00 date: ?? to ? e ? 01 ? ? 01 ? ?? to ? e ? 01 ? ? 01 ?
rev. 1.00 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 3 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom table of contents eates cpu featu ? es .............................................................................................................................. 7 pe ? iphe ? al featu ? es ...................................................................................................................... 7 gene?al des??iption ............................................................................................. 8 sele?tion ta?le ..................................................................................................... 8 blo?k diag?am ...................................................................................................... 9 pin assignment ........... ......................................................................................... 9 pin des??iptions ................................................................................................ 11 a?solute maximum ratings .............................................................................. 18 d.c. cha?a?te?isti?s ........................................................................................... 18 a.c. cha?a?te?isti?s ........................................................................................... ?0 hirc ele?t?i?al cha?a?te?isti?s ... ..................................................................... ?1 a/d conve?te? ele?t?i?al cha?a?te?isti?s ........... .............................................. ?? lvd/lvr ele?t?i?al cha?a?te?isti?s .................................................................. ?3 compa?ato? ele?t?i?al cha?a?te?isti?s ............................................................ ?3 softwa?e cont?olled lcd d?ive? ele?t?i?al cha?a?te?isti?s ........................... ?? powe?-on reset cha?a?te?isti?s ........... ............................................................ ?? system a??hite?tu?e .......................................................................................... ?5 clo ? king and pipelining .............................................................................................................. ? 5 p ? og ? am counte ? ........................................................................................................................ ? 6 sta ? k .......................................................................................................................................... ? 7 a ? ithmeti ? and logi ? unit C alu ................................................................................................ ? 7 flash p?og?am memo?y ..................................................................................... ?8 st ? u ? tu ? e ..................................................................................................................................... ? 8 spe ? ial ve ? to ? s .......................................................................................................................... ? 8 look-up ta ? le ............. ................................................................................................................ ? 9 ta ? le p ? og ? am example ............................................................................................................. ? 9 in ci ?? uit p ? og ? amming C icp .................................................................................................... 30 ? n-chip de ? ug suppo ? t C ? cds .............................................................................................. 31 data memo?y ...................................................................................................... 3? st ? u ? tu ? e ..................................................................................................................................... 3 ? spe?ial fun?tion registe? des??iption ............................................................ 3? indi ? e ? t add ? essing registe ? s C iar0 ? iar1 .............................................................................. 3 ? memo ? y pointe ? s C mp0 ? mp1 ................................................................................................... 3 ? bank pointe ? C bp ...................................................................................................................... 35 a ?? umulato ? C acc .................................................................................................................... 35 p ? og ? am counte ? low registe ? C pcl ....................................................................................... 35 look-up ta ? le registe ? s C tblp ? tbhp ? tblh .......................................................................... 35 status registe ? C status ......................................................................................................... 36
rev. 1.00 ? ??to?e? 01? ?01? rev. 1.00 3 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom eeprom data memory ........... ........................................................................... 38 eepr ? m data memo ? y st ? u ? tu ? e ............................................................................................. 38 eepr ? m registe ? s ............ ....................................................................................................... 38 reading data f ? om the eepr ? m .............................................................................................. ? 0 w ? iting data to the eepr ? m ..................................................................................................... ? 0 w ? ite p ? ote ? tion .......................................................................................................................... ? 0 eepr ? m inte ?? upt ............. ........................................................................................................ ? 0 p ? og ? amming conside ? ations ............. ........................................................................................ ? 1 oscillator ............................................................................................................ 42 ? s ? illato ? ? ve ? view ............. ....................................................................................................... ?? system clock confgurations ..................................................................................................... ?? exte ? nal c ? ystal/ce ? ami ? ? s ? illato ? C hxt ................................................................................ ? 3 inte ? nal high speed rc ? s ? illato ? C hirc ................................................................................ ?? exte ? nal 3 ? .768 khz c ? ystal ? s ? illato ? C lxt ............. ............................................................... ?? inte ? nal 3 ? khz ? s ? illato ? C lirc ................................................................................................ ? 5 supplementa ? y ? s ? illato ? s ......................................................................................................... ? 5 operating modes and system clocks ............................................................. 46 system clo ? ks ........................................................................................................................... ? 6 system ? pe ? ation modes ........................................................................................................... ? 7 cont ? ol registe ? s ....................................................................................................................... ? 8 fast wake-up ............................................................................................................................. 50 ? pe ? ating mode swit ? hing ......................................................................................................... 51 stand ? y cu ?? ent conside ? ations ................................................................................................ 55 wake-up ..................................................................................................................................... 55 p ? og ? amming conside ? ations ............. ........................................................................................ 56 watchdog timer ........... ...................................................................................... 56 wat ? hdog time ? clo ? k sou ?? e ................................................................................................... 56 wat ? hdog time ? cont ? ol registe ? ............. ................................................................................. 56 wat ? hdog time ? ? pe ? ation ........................................................................................................ 58 reset and initialisation ...................................................................................... 59 reset fun ? tions ............. ............................................................................................................ 59 reset initial conditions .............................................................................................................. 61 input/output ports ............................................................................................. 65 pull-high resisto ? s ..................................................................................................................... 66 po ? t a wake-up ............. ............................................................................................................. 66 i/ ? po ? t cont ? ol registe ? s .......................................................................................................... 67 i/ ? po ? t sou ?? e cu ?? ent cont ? ol ................................................................................................. 67 pin- ? emapping fun ? tions ........................................................................................................... 69 i/ ? pin st ? u ? tu ? es ....................................................................................................................... 70 p ? og ? amming conside ? ations ............. ........................................................................................ 71
rev. 1.00 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 5 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom timer modules C tm .......... ................................................................................ 72 int ? odu ? tion ................................................................................................................................ 7 ? tm ? pe ? ation ............. ................................................................................................................ 7 ? tm clo ? k sou ?? e ............. ........................................................................................................... 73 tm inte ?? upts .............................................................................................................................. 73 tm exte ? nal pins ........................................................................................................................ 73 tm input/ ? utput pin cont ? ol registe ? ........................................................................................ 7 ? p ? og ? amming conside ? ations ............. ........................................................................................ 76 compact type tm C ctm .................................................................................. 77 compa ? t tm ? pe ? ation .............................................................................................................. 77 compa ? t type tm registe ? des ?? iption ..................................................................................... 78 compa ? t type tm ? pe ? ation modes ......................................................................................... 8 ? standard type tm C stm .......... ........................................................................ 88 standa ? d tm ? pe ? ation ............. ................................................................................................. 88 standa ? d type tm registe ? des ?? iption .................................................................................... 89 standa ? d type tm ? pe ? ation modes ......................................................................................... 93 periodic type tm C ptm .................................................................................. 103 pe ? iodi ? tm ? pe ? ation ............. ................................................................................................ 103 pe ? iodi ? type tm registe ? des ?? iption .................................................................................... 10 ? pe ? iodi ? type tm ? pe ? ation modes ......................................................................................... 109 analog to digital converter .......... .................................................................. 118 a/d ? ve ? view ............. .............................................................................................................. 118 a/d conve ? te ? registe ? des ?? iption ......................................................................................... 119 a/d input pins ............. ............................................................................................................. 1 ? 5 a/d refe ? en ? e voltage ............. ................................................................................................ 1 ? 5 a/d ? pe ? ation .......................................................................................................................... 1 ? 5 conve ? sion rate and timing diag ? am ..................................................................................... 1 ? 6 summa ? y of a/d conve ? sion steps ............. ............................................................................. 1 ? 7 p ? og ? amming conside ? ations ............. ...................................................................................... 1 ? 8 a/d t ? ansfe ? fun ? tion ............. ................................................................................................. 1 ? 8 a/d p ? og ? amming examples .................................................................................................... 1 ? 9 serial interface module C sim ......................................................................... 131 spi inte ? fa ? e ............................................................................................................................ 131 spi registe ? s ............. .............................................................................................................. 13 ? spi communi ? ation ................................................................................................................. 135 i ? c inte ? fa ? e ............ ................................................................................................................. 137 i ? c registe ? s ............................................................................................................................ 138 i ? c bus communi ? ation ........................................................................................................... 1 ?? i ? c time-out cont ? ol ................................................................................................................. 1 ? 5
rev. 1.00 ? ??to?e? 01? ?01? rev. 1.00 5 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom comparators .................................................................................................... 147 compa ? ato ? ? pe ? ation ............................................................................................................. 1 ? 7 compa ? ato ? inte ?? upt ................................................................................................................ 1 ? 7 p ? og ? amming conside ? ations ............. ...................................................................................... 1 ? 7 scom/sseg function for lcd ........... ............................................................ 149 lcd ? pe ? ation ............. ............................................................................................................ 1 ? 9 lcd cont ? ol registe ? s ............................................................................................................. 151 uart interface ................................................................................................. 156 uart exte ? nal pin ................................................................................................................... 157 uart data t ? ansfe ? s ? heme ................................................................................................... 157 uart status and cont ? ol registe ? s ......................................................................................... 157 baud rate gene ? ato ? ............................................................................................................... 163 uart setup and cont ? ol .......................................................................................................... 16 ? uart t ? ansmitte ? ..................................................................................................................... 165 uart re ? eive ? ............. ........................................................................................................... 166 managing re ? eive ? e ?? o ? s ....................................................................................................... 168 uart inte ?? upt st ? u ? tu ? e .......................................................................................................... 169 uart powe ? down and wake-up ............................................................................................ 170 low voltage detector C lvd .......... ................................................................. 171 lvd registe ? ............. ............................................................................................................... 171 lvd ? pe ? ation .......................................................................................................................... 17 ? interrupts .......................................................................................................... 173 inte ?? upt registe ? s .................................................................................................................... 173 inte ?? upt ? pe ? ation ................................................................................................................... 180 exte ? nal inte ?? upt ............. ......................................................................................................... 18 ? compa ? ato ? inte ?? upt C ht66f0185 ......................................................................................... 18 ? multi-fun ? tion inte ?? upt ............................................................................................................. 18 ? a/d conve ? te ? inte ?? upt ............................................................................................................ 183 time base inte ?? upt .................................................................................................................. 183 se ? ial inte ? fa ? e module inte ?? upt .............................................................................................. 18 ? uart t ? ansfe ? inte ?? upt C ht66f0185 .................................................................................... 18 ? lvd inte ?? upt ............................................................................................................................ 185 eepr ? m inte ?? upt ............. ...................................................................................................... 185 tm inte ?? upt ............. ................................................................................................................. 185 inte ?? upt wake-up fun ? tion ...................................................................................................... 186 p ? og ? amming conside ? ations ............. ...................................................................................... 186 confguration options ..................................................................................... 187 application circuits ........... .............................................................................. 187
rev. 1.00 6 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 7 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom instruction set .................................................................................................. 188 int ? odu ? tion .............................................................................................................................. 188 inst ? u ? tion timing ..................................................................................................................... 188 moving and t ? ansfe ?? ing data .................................................................................................. 188 a ? ithmeti ? ? pe ? ations ............................................................................................................... 188 logi ? al and rotate ? pe ? ation .................................................................................................. 189 b ? an ? hes and cont ? ol t ? ansfe ? ................................................................................................ 189 bit ? pe ? ations .......................................................................................................................... 189 ta ? le read ? pe ? ations ............................................................................................................ 189 ? the ? ? pe ? ations ............. ......................................................................................................... 189 instruction set summary .......... ...................................................................... 190 ta ? le conventions .................................................................................................................... 190 instruction defnition ....................................................................................... 192 package information ....................................................................................... 201 ? 0-pin s ? p (300mil) ? utline dimensions ................................................................................ ? 0 ? ? 0-pin ss ? p (150mil) ? utline dimensions .............................................................................. ? 03 ?? -pin s ? p (300mil) ? utline dimensions ................................................................................ ? 0 ? ?? -pin ss ? p (150mil) ? utline dimensions .............................................................................. ? 05 ? 8-pin s ? p (300mil) ? utline dimensions ................................................................................ ? 06 ? 8-pin ss ? p (150mil) ? utline dimensions .............................................................................. ? 07
rev. 1.00 6 ??to?e? 01? ?01? rev. 1.00 7 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom features cpu features ? operating voltage f sys = 8mhz : 2.2v~5.5v f sys =12mhz : 2.7v~5.5v f sys =20mhz : 4.5v~5.5v ? up to 0.2s instruction cycle with 20mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? oscillator type external high speed crystal C hxt external 32.768khz crystal C lxt internal high speed rc C hirc internal 32khz rc C lirc ? fully integrated internal 8/12/16 mhz oscillator requires no external components ? multi-mode operation: normal, slow, idle and sleep ? all instructions executed in one to three instruction cycles ? table read instructions ? 63 powerful instructions ? 8-level subroutine nesting ? bit manipulation instruction peripheral features ? program memory: up to 4k16 ? data memory: up to 2568 ? eeprom memory: up to 1288 ? watchdog t imer function ? up to 26 bidirectional i/o lines ? two external interrupt lines shared with i/o pins ? multiple t imer modules for time measure, input capture, compare match output, pwm output function or single pulse output function ? serial interfaces module C sim for spi or i 2 c ? software controlled 6-scom/sseg and 18-sseg lines lcd driver with 1/3 bias ? programmable i/o port source current for led applications ? dual t ime-base functions for generation of fxed time interrupt signals ? 8-channel 12-bit resolution a/d converter ? one comparator function C available in ht66f0185 ? fully-duplex u niversal a synchronous receiver and t ransmitter interface C u art, available in ht66f0185 ? low voltage reset function ? low voltage detect function ? flash program memory can be re-programmed up to 100,000 times ? flash program memory data retention > 10 years ? eeprom data memory can be re-programmed up to 1,000,000 times ? eeprom data memory data retention > 10 years ? wide range of available package types
rev. 1.00 8 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 9 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom general description the series of devices are flash memory a/d type 8-bit high performance risc architecture microcontroller. of fering users the convenience of flash memory multi-programming features, these devices also include a wide range of functions and features. other memory includes an area of ram data memory as well as an area of eeprom memory for storage of non-volatile data such as serial numbers, calibratuib data, etc. analog features include a multi-cha nnel 12-bit a/d converter and a comparator functions. multiple and extremely flexible t imer modules provide timing, pulse generation and pwm generation functions. prot ective fe atures suc h a s a n i nternal w atchdog t imer, l ow v oltage re set a nd l ow voltage detector coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a full choice of hxt , lxt , hirc and lirc oscillator functions are provided including a fully integrated system oscillator which requires no ext ernal com ponents for i ts i mplementation. the abi lity t o operat e and swit ch dynam ically between a range of operating modes using dif ferent clock sources gives users the ability to optimise microcontroller operation and minimize power consumption. the inclusion of fexible i/o programming features, t ime-base functions along with many other features e nsure t hat t he de vice wi ll fnd e xcellent use i n a pplications suc h a s e lectronic m etering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others. selection table most features are common to all devices. the main features distinguishing them are memory capacity, i /o c ount, t imer mo dule f eatures, sse g c ount, l ed c ount, uar t a nd p ackage t ypes. t he following table summarises the main features of each device. part no. program memory data memory data eeprom i/o external interrupt a/d timer module HT66F0175 ? k 16 1 ? 8 8 6 ? 8 ?? ? 1 ? - ? it 8 10- ? it ptm ? ht66f0185 ? k 16 ? 56 8 1 ? 8 8 ? 6 ? 1 ? - ? it 8 16- ? it ctm 1 16- ? it stm 1 10- ? it ptm 1 part no. time base sim uart cmp scom/ sseg sseg led stack package HT66F0175 ? 6 1 ? ?? 8 ? 0/ ?? s ? p/ss ? p ht66f0185 ? 6 18 ? 6 8 ?? / ? 8s ? p/ss ? p note: as devices exist in more than one package format, the table refects the situation for the package with the most pins.
rev. 1.00 8 ??to?e? 01? ?01? rev. 1.00 9 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom block diagram 8-bit risc mcu core i/o timer modules flash program memory eeprom data memory flash/eeprom programming circuitry time base sim (spi/i 2 c) low voltage reset watchdog timer low voltage detect interrupt controller reset circuit external hxt/lxt oscillators 12-bit a/d converter ram data memory sseg/ scom uart internal hirc/lirc oscillators for ht66f0185 + for ht66f0185 comparator pin assignment HT66F0175/ht66v0175 20 sop-a/ssop-a ?0 19 18 17 16 15 1? 13 1? 11 1 ? 3 ? 5 6 7 8 9 10 vss&avss pc0/sseg17/?sc1 pc1/sseg18/?sc? pc?/sd?/sseg0/sc?m0 pa0/tp0/icpda/?cdsda pa?/icpck/?cdsck pa3/[sdi/sda]/sseg3/sc?m3 pb6/[sck/scl]/sseg?/sc?m? pa1/[sd?]/scs/sseg?/sc?m? pb5/[scs]/sseg5/sc?m5 vdd&avdd pb0/int0/sseg16/an0/xt1 pb1/int1/sseg15/an1/xt? pb?/tck0/sseg1?/an? pa?/tck1/sseg13/an3 pa5/sseg10/an?/vrefi pa6/sseg9/an5/vref pa7/tp1/sseg8/an6 pb3/sseg7/an7 pb?/cl?/sseg6
rev. 1.00 10 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 11 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66v0175 24 sop-a/ssop-a ?? ?3 ?? ?1 ?0 19 18 17 16 15 1? 13 1 ? 3 ? 5 6 7 8 9 10 11 1? vdd&avdd pb0/int0/sseg16/an0/xt1 pb1/int1/sseg15/an1/xt? pb?/tck0/sseg1?/an? pa?/tck1/sseg13/an3 pa5/sseg10/an?/vrefi pa6/sseg9/an5/vref pa7/tp1/sseg8/an6 pb3/sseg7/an7 pb?/cl?/sseg6 pc5/[int1]/sseg11 pc6/[int0]/sseg1? vss&avss pc0/sseg17/?sc1 pc1/sseg18/?sc? pc?/sd?/sseg0/sc?m0 pa0/tp0/icpda/pcdsda pa1/[sd?]/scs/sseg?/sc?m? pa?/icpck/?cdsck pa3/[sdi/sda]/sseg3/sc?m3 pb6/[sck/scl]/sseg?/sc?m? pb5/[scs]/sseg5/sc?m5 pc3/sdi/sda/sseg19 pc?/sck/scl/sseg1/sc?m1 ht66f0185/ht66v0185 24 sop-a/ssop-a ?? ?3 ?? ?1 ?0 19 18 17 16 15 1? 13 1 ? 3 ? 5 6 7 8 9 10 11 1? vdd&avdd pb0/int0/sseg18/an0/xt1 pb1/int1/sseg17/an1/xt? pb?/tck0/sseg16/an? pa?/tck1/sseg15/an3 pa5/sseg10/an?/vrefi pa6/tck?/sseg9/an5/vref pa7/tp1/sseg8/an6 pb3/[tx]/tp?/sseg7/an7 pb?/[rx]/cl?/sseg6 pd1/rx/sseg1? pd?/tx/sseg13 vss&avss pc0/sseg19/?sc1 pc1/sseg?0/?sc? pc?/[sd?]/sseg0/sc?m0 pa0/tp0/icpda/?cdsda pa1/[sd?]/sseg?/sc?m? pa?/icpck/?cdsck pa3/[sdi/sda]/cx/sseg3/sc?m3 pb6/[sck/scl]/ c+/sseg?/sc?m? pb5/[scs]/c-/sseg5/sc?m5 pc?/sdi/sda/sseg?? pc5/sck/scl/sseg1/sc?m1 ht66f0185/ht66v0185 28 sop-a/ssop-a ?8 ?7 ?6 ?5 ?? ?3 ?? ?1 ?0 19 18 17 16 15 1 ? 3 ? 5 6 7 8 9 10 11 1? 13 1? vdd&avdd pb0/int0/sseg18/an0/xt1 pb1/int1/sseg17/an1/xt? pb?/tck0/sseg16/an? pa?/tck1/sseg15/an3 pa5/sseg10/an?/vrefi pa6/tck?/sseg9/an5/vref pa7/tp1/sseg8/an6 pb3/[tx]/tp?/sseg7/an7 pb?/[rx]/cl?/sseg6 pd0/sseg11 pd1/rx/sseg1? pd?/tx/sseg13 pd3/sseg1? vss&avss pc0/sseg19/?sc1 pc1/sseg?0/?sc? pc?/[sd?]/sseg0/sc?m0 pa0/tp0/icpda/?cdsda pa1/[sd?]/sseg?/sc?m? pa?/icpck/?cdsck pa3/[sdi/sda]/cx/sseg3/sc?m3 pb6/[sck/scl]/c+/sseg?/sc?m? pb5/[scs]/c-/sseg5/sc?m5 pc3/sd?/sseg?1 pc?/sdi/sda/sseg?? pc5/sck/scl/sseg1/sc?m1 pc6/scs/sseg?3 note: 1. if the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the / sign can be used for higher priority. 2. vdd&a vdd means the vdd and a vdd are the double bonding. 3. vss&a vss means the vss and a vss are the double bonding. 4. the ocdsda and ocdsck pins are the ocds dedicated pins and only available for the ht66v01x5 device which is the ocds ev chip for the ht66f01x5 device.
rev. 1.00 10 ??to?e? 01? ?01? rev. 1.00 11 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom pin descriptions with the exception of the power pins, all pins on these devices can be referenced by their port name, e.g. p a0, p a1 etc, which refer to the digital i/o function of the pins. however these port pins are also sha red wi th ot her func tion suc h a s t he ana log t o di gital conve rter, t imer modul e pi ns, e tc. the function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. HT66F0175 pad name function opt i/t o/t description pa0/tp0/icpda/ ? cdsda pa0 pawu papu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up and wake-up. tp0 tmpc st cm ? s tm0 input/output icpda st cm ? s icp data/add ? ess pin ? cdsda st cm ? s ? cds data/add ? ess pin ? fo ? ev ? hip only. pa1/[sd ? ]/ scs/ sseg ? /sc ? m ? pa1 pawu papu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up and wake-up. [sd ? ] slcdc0 simc0 ifs cm ? s spi data output scs slcdc0 simc0 ifs st cm ? s spi slave sele ? t sseg ? slcdc0 slcdc1 sseg softwa ? e ? ont ? olled lcd segment output sc ? m ? slcdc0 slcdc1 sc ? m softwa ? e ? ont ? olled lcd ? ommon output pa ? /icpck/ ? cdsck pa ? pawu papu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up and wake-up. icpck st cm ? s icp clo ? k pin ? cdsck st ? cds clo ? k pin ? fo ? ev ? hip only. pa3/[sdi/sda]/ sseg3/sc ? m3 pa3 pawu papu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up and wake-up. [sdi] slcdc0 simc0 ifs st spi data input [sda] slcdc0 simc0 ifs st nm ? s i ? c add ? ess/data line sseg3 slcdc0 slcdc1 sseg softwa ? e ? ont ? olled lcd segment output sc ? m3 slcdc0 slcdc1 sc ? m softwa ? e ? ont ? olled lcd ? ommon output pa ? /tck1/ sseg13/an3 pa ? pawu papu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up and wake-up. tck1 tm1c0 st tm1 input sseg13 slcdc ? sseg softwa ? e ? ont ? olled lcd segment output an3 acerl an a/d conve ? te ? analog input pa5/sseg10/ an ? /vrefi pa5 pawu papu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up and wake-up. sseg10 slcdc ? sseg softwa ? e ? ont ? olled lcd segment output an ? acerl an a/d conve ? te ? analog input vrefi sadc ? an a/d conve ? te ? pga voltage input
rev. 1.00 1 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 13 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom pad name function opt i/t o/t description pa6/sseg9/an5/ vref pa6 pawu papu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up and wake-up. sseg9 slcdc ? sseg softwa ? e ? ont ? olled lcd segment output an5 acerl an a/d conve ? te ? analog input vref sadc ? a ? a/d conve ? te ? ? efe ? en ? e voltage output pa7/tp1/sseg8/ an6 pa7 pawu papu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up and wake-up. tp1 tmpc st cm ? s tm1 input/output sseg8 slcdc ? sseg softwa ? e ? ont ? olled lcd segment output an6 acerl an a/d conve ? te ? analog input pb0/int0/ sseg16/an0/xt1 pb0 pbpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. int0 ifs integ st exte ? nal inte ?? upt 0 sseg16 slcdc3 sseg softwa ? e ? ont ? olled lcd segment output an0 acerl an a/d conve ? te ? analog input xt1 c ? lxt lxt os ? illato ? pin pb1/int1/ sseg15/an1/xt ? pb1 pbpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. int1 ifs integ st exte ? nal inte ?? upt 1 sseg15 slcdc3 sseg softwa ? e ? ont ? olled lcd segment output an1 acerl an a/d conve ? te ? analog input xt ? c ? lxt lxt os ? illato ? pin pb ? /tck0/ sseg1 ? /an ? pb ? pbpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. tck0 tm0c0 st tm0 input sseg1 ? slcdc3 sseg softwa ? e ? ont ? olled lcd segment output an ? acerl an a/d conve ? te ? analog input pb3/sseg7/an7 pb3 pbpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. sseg7 slcdc ? sseg softwa ? e ? ont ? olled lcd segment output an7 acerl an a/d conve ? te ? analog input pb ? /cl ? /sseg6 pb ? pbpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. cl ? tmpc cm ? s system ? lo ? k output sseg6 slcdc ? sseg softwa ? e ? ont ? olled lcd segment output pb5/[scs]/ sseg5/sc ? m5 pb5 pbpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. [scs] slcdc0 simc0 ifs cm ? s system ? lo ? k output sseg5 slcdc1 sseg softwa ? e ? ont ? olled lcd segment output sc ? m5 slcdc1 sc ? m softwa ? e ? ont ? olled lcd ? ommon output pb6/[sck/scl]/ sseg ? /sc ? m ? pb6 pbpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. [sck] simc0 ifs st cm ? s spi se ? ial ? lo ? k [scl] simc0 ifs st nm ? s i ? c ? lo ? k line sseg ? slcdc1 sseg softwa ? e ? ont ? olled lcd segment output sc ? m ? slcdc1 sc ? m softwa ? e ? ont ? olled lcd ? ommon output pc0/sseg17/ ? sc1 pc0 pcpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. sseg17 slcdc3 sseg softwa ? e ? ont ? olled lcd segment output ? sc1 c ? hxt hxt os ? illato ? pin pc1/sseg18/ ? sc ? pc1 pcpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. sseg18 slcdc3 sseg softwa ? e ? ont ? olled lcd segment output ? sc ? c ? hxt hxt os ? illato ? pin
rev. 1.00 1? ??to?e? 01? ?01? rev. 1.00 13 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom pad name function opt i/t o/t description pc ? /sd ? /sseg0/ sc ? m0 pc ? pcpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. sd ? simc0 ifs cm ? s spi data output sseg0 slcdc0 slcdc1 sseg softwa ? e ? ont ? olled lcd segment output sc ? m0 slcdc0 slcdc1 sc ? m softwa ? e ? ont ? olled lcd ? ommon output pc3/sdi/sda/ sseg19 pc3 pcpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. sdi simc0 ifs st spi data input sda simc0 ifs st nm ? s i ? c data line sseg19 slcdc3 sseg softwa ? e ? ont ? olled lcd segment output pc ? /sck/scl/ sseg1/sc ? m1 pc ? pcpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. sck simc0 ifs st cm ? s spi se ? ial ? lo ? k scl simc0 ifs st nm ? s i ? c ? lo ? k line sseg1 slcdc0 slcdc1 sseg softwa ? e ? ont ? olled lcd segment output sc ? m1 slcdc0 slcdc1 sc ? m softwa ? e ? ont ? olled lcd ? ommon output pc5/[int1]/ sseg11 pc5 pcpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. [int1] integ ifs st exte ? nal inte ?? upt 1 sseg11 slcdc ? sseg softwa ? e ? ont ? olled lcd segment output pc6/[int0]/ sseg1 ? pc6 pcpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. [int0] integ ifs st exte ? nal inte ?? upt 0 sseg1 ? slcdc ? sseg softwa ? e ? ont ? olled lcd segment output vdd&avdd vdd pwr positive powe ? supply avdd pwr a/d ? onve ? te ? positive powe ? supply vss&avss vss pwr negative powe ? supply ? g ? ound. avss pwr a/d ? onve ? te ? negative powe ? supply ? g ? ound. note: i/t: input type; o/t: output type; opt: optional by confguration option (co) or register option; co: confguration option; st: schmitt t rigger input; an: analog input; cmos: cmos output; nmos: nmos output; ao: analog output; sseg: software controlled lcd seg; scom: software controlled lcd com; hxt: high frequency crystal oscillator; lxt: low frequency crystal oscillator pwr: power * the a vdd pin is internally bonded together with the vdd pin while the a vss pin is internally bonded together with the vss pin. as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. ht66f0185
rev. 1.00 1 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 15 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom pad name function opt i/t o/t description pa0/tp0/icpda/ ? cdsda pa0 pawu papu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up and wake-up. tp0 tmpc st cm ? s tm0 input/output icpda st cm ? s icp data/add ? ess pin ? cdsda st cm ? s ? cds data/add ? ess pin ? fo ? ev ? hip only. pa1/[sd ? ]/sseg ? / sc ? m ? pa1 pawu papu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up and wake-up. [sd ? ] slcdc0 simc0 ifs cm ? s spi data output sseg ? slcdc0 slcdc1 sseg softwa ? e ? ont ? olled lcd segment output sc ? m ? slcdc0 slcdc1 sc ? m softwa ? e ? ont ? olled lcd ? ommon output pa ? /icpck/ ? cdsck pa ? pawu papu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up and wake-up. icpck st cm ? s icp clo ? k pin ? cdsck st ? cds clo ? k pin ? fo ? ev ? hip only. pa3/[sdi/sda]/cx/ sseg3/sc ? m3 pa3 pawu papu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up and wake-up. [sdi] slcdc0 simc0 ifs st spi data input [sda] slcdc0 simc0 ifs st nm ? s i ? c add ? ess/data line cx cpc cm ? s compa ? ato ? output sseg3 slcdc0 slcdc1 sseg softwa ? e ? ont ? olled lcd segment output sc ? m3 slcdc0 slcdc1 sc ? m softwa ? e ? ont ? olled lcd ? ommon output pa ? /tck1/ sseg15/an3 pa ? pawu papu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up and wake-up. tck1 tm1c0 st tm1 input sseg15 slcdc3 sseg softwa ? e ? ont ? olled lcd segment output an3 acerl an a/d conve ? te ? analog input pa5/sseg10/an ? / vrefi pa5 pawu papu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up and wake-up. sseg10 slcdc ? sseg softwa ? e ? ont ? olled lcd segment output an ? acerl an a/d conve ? te ? analog input vrefi sadc ? an a/d conve ? te ? pga voltage input pa6/tck ? /sseg9/ an5/vref pa6 pawu papu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up and wake-up. tck ? tm ? c0 st tm ? input sseg9 slcdc ? sseg softwa ? e ? ont ? olled lcd segment output an5 acerl an a/d conve ? te ? analog input vref sadc ? a ? a/d conve ? te ? ? efe ? en ? e voltage output pa7/tp1/sseg8/ an6 pa7 pawu papu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up and wake-up. tp1 tmpc st cm ? s tm1 input/output sseg8 slcdc ? sseg softwa ? e ? ont ? olled lcd segment output an6 acerl an a/d conve ? te ? analog input
rev. 1.00 1? ??to?e? 01? ?01? rev. 1.00 15 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom pad name function opt i/t o/t description pb0/int0/sseg18/ an0/xt1 pb0 pbpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. int0 ifs integ st exte ? nal inte ?? upt 0 sseg18 slcdc3 sseg softwa ? e ? ont ? olled lcd segment output an0 acerl an a/d conve ? te ? analog input xt1 c ? lxt lxt os ? illato ? pin pb1/int1/sseg17/ an1/xt ? pb1 pbpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. int1 ifs integ st exte ? nal inte ?? upt 1 sseg17 slcdc3 sseg softwa ? e ? ont ? olled lcd segment output an1 acerl an a/d conve ? te ? analog input xt ? c ? lxt lxt os ? illato ? pin pb ? /tck0/ sseg16/an ? pb ? pbpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. tck0 tm0c0 st tm0 input sseg16 slcdc3 sseg softwa ? e ? ont ? olled lcd segment output an ? acerl an a/d conve ? te ? analog input pb3/[tx]/tp ? / sseg7/an7 pb3 pbpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. [tx] ucr1 ucr ? cm ? s uart tx se ? ial data output tp ? tmpc st cm ? s tm ? input/output sseg7 slcdc ? sseg softwa ? e ? ont ? olled lcd segment output an7 acerl an a/d conve ? te ? analog input pb ? /[rx]/cl ? / sseg6 pb ? pbpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. [rx] ucr1 ucr ? st uart rx se ? ial data input cl ? tmpc cm ? s system ? lo ? k output sseg6 slcdc ? sseg softwa ? e ? ont ? olled lcd segment output pb5/[scs]/c-/ sseg5/sc ? m5 pb5 pbpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. [scs] slcdc0 simc0 ifs st cm ? s system ? lo ? k output c- cpc an compa ? ato ? input sseg5 slcdc1 sseg softwa ? e ? ont ? olled lcd segment output sc ? m5 slcdc1 sc ? m softwa ? e ? ont ? olled lcd ? ommon output pb6/[sck/scl]/c+/ sseg ? /sc ? m ? pb6 pbpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. [sck] simc0 ifs st cm ? s spi se ? ial ? lo ? k [scl] simc0 ifs st nm ? s i ? c ? lo ? k line c+ cpc an compa ? ato ? input sseg ? slcdc1 sseg softwa ? e ? ont ? olled lcd segment output sc ? m ? slcdc1 sc ? m softwa ? e ? ont ? olled lcd ? ommon output pc0/sseg19/ ? sc1 pc0 pcpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. sseg19 slcdc3 sseg softwa ? e ? ont ? olled lcd segment output ? sc1 c ? hxt hxt os ? illato ? pin pc1/sseg ? 0/ ? sc ? pc1 pcpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. sseg ? 0 slcdc3 sseg softwa ? e ? ont ? olled lcd segment output ? sc ? c ? hxt hxt os ? illato ? pin
rev. 1.00 16 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 17 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom pad name function opt i/t o/t description pc ? /[sd ? ]/sseg0/ sc ? m0 pc ? pcpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. [sd ? ] simc0 ifs cm ? s spi data output sseg0 slcdc0 slcdc1 sseg softwa ? e ? ont ? olled lcd segment output sc ? m0 slcdc0 slcdc1 sc ? m softwa ? e ? ont ? olled lcd ? ommon output pc3/sd ? /sseg ? 1 pc3 pcpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. sd ? simc0 ifs cm ? s spi data output sseg ? 1 slcdc3 sseg softwa ? e ? ont ? olled lcd segment output pc ? /sdi/sda// sseg ?? pc ? pcpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. sdi simc0 ifs st spi data input sda simc0 ifs st nm ? s i ? c data line sseg ?? slcdc ? sseg softwa ? e ? ont ? olled lcd segment output pc5/sck/scl/ sseg1/sc ? m1 pc5 pcpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. sck simc0 ifs st cm ? s spi se ? ial ? lo ? k scl simc0 ifs st nm ? s i ? c ? lo ? k line sseg1 slcdc0 slcdc1 sseg softwa ? e ? ont ? olled lcd segment output sc ? m1 slcdc0 slcdc1 sc ? m softwa ? e ? ont ? olled lcd ? ommon output pc6/scs /sseg ? 3 pc6 pcpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. scs slcdc0 simc0 ifs st cm ? s system ? lo ? k output sseg ? 3 slcdc ? sseg softwa ? e ? ont ? olled lcd segment output pd0/sseg11 pd0 pdpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. sseg11 slcdc ? sseg softwa ? e ? ont ? olled lcd segment output pd1/rx/sseg1 ? pd1 pdpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. rx ucr1 ucr ? st uart rx se ? ial data input sseg1 ? slcdc ? sseg softwa ? e ? ont ? olled lcd segment output pd ? /tx/sseg13 pd ? pdpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. tx ucr1 ucr ? cm ? s uart tx se ? ial data output sseg13 slcdc ? sseg softwa ? e ? ont ? olled lcd segment output pd3/sseg1 ? pd3 pdpu st cm ? s gene ? al pu ? pose i/ ? . registe ? ena ? led pull-up. sseg1 ? slcdc3 sseg softwa ? e ? ont ? olled lcd segment output vdd&avdd vdd pwr positive powe ? supply avdd pwr a/d ? onve ? te ? positive powe ? supply vss&avss vss pwr negative powe ? supply ? g ? ound. avss pwr a/d ? onve ? te ? negative powe ? supply ? g ? ound. note: i/t: input type; o/t: output type; opt: optional by confguration option (co) or register option; co: confguration option; st: schmitt t rigger input; an: analog input; cmos: cmos output; nmos: nmos output; ao: analog output; sseg: software controlled lcd seg; scom: software controlled lcd com; hxt: high frequency crystal oscillator; lxt: low frequency crystal oscillator
rev. 1.00 16 ??to?e? 01? ?01? rev. 1.00 17 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom pwr: power * the a vdd pin is internally bonded together with the vdd pin while the a vss pin is internally bonded together with the vss pin. as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins.
rev. 1.00 18 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 19 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom absolute maximum ratings supply v oltage .............. .................................................................................... v ss ?0.3v to v ss +6.0v input v oltage .............. ....................................................................................... v ss ?0.3v to v dd +0.3v storage t emperature ............... ....................................................................................... -50?c to 125?c operating t emperature .............. ....................................................................................... -40?c to 85?c i oh t otal .............. ......................................................................................................................... -80ma i ol t otal .............. ................................................................................................... ....................... 80ma total power dissipation .............. ............................................................................................. 500mw note: thes e are s tress ratings only . s tresses exceeding the range s pecified under abs olute maximum ra tings m ay c ause subst antial da mage t o t hese de vices. funct ional opera tion of these devices at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect devices reliability. d.c. characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v dd ? pe ? ating voltage (hxt) f sys = f hxt =8mhz ? . ? 5.5 v f sys = f hxt =1 ? mhz ? .7 5.5 v f sys = f hxt =16mhz ? .5 5.5 v f sys = f hxt = ? 0mhz ? .5 5.5 v ? pe ? ating voltage (hirc) f sys = f hirc =8mhz ? . ? 5.5 v f sys = f hirc =1 ? mhz ? .7 5.5 v f sys = f hirc =16mhz ? .5 5.5 v i dd ? pe ? ating cu ?? ent (hxt) 3v f sys =f h = f hxt =8mhz no load ? all pe ? iphe ? als off 1.0 1.5 ma 5v ? .0 3.0 ma 3v f sys =f h = f hxt =1 ? mhz no load ? all pe ? iphe ? als off 1.5 ? .75 ma 5v 3.0 ? .5 ma 5v f sys =f h = f hxt =16mhz ? no load ? all pe ? iphe ? als off ? .5 7.0 ma 5v f sys =f h = f hxt = ? 0mhz ? no load ? all pe ? iphe ? als off 5.5 8.5 ma ? pe ? ating cu ?? ent (hirc) 3v f sys =f h = f hirc =8mhz no load ? all pe ? iphe ? als off 0.8 1. ? ma 5v 1.6 ? . ? ma 3v f sys =f h = f hirc =1 ? mhz no load ? all pe ? iphe ? als off 1. ? 1.8 ma 5v ? . ? 3.6 ma 5v f sys =f h = f hirc =16mhz no load ? all pe ? iphe ? als off ? .5 7.0 ma ? pe ? ating cu ?? ent (lxt) 3v f sys =f sub =f lxt =3 ? .768khz no load ? all pe ? iphe ? als off 10 ? 0 5v 30 50 ? pe ? ating cu ?? ent (lirc) 3v f sys =f sub =f lirc =3 ? khz no load ? all pe ? iphe ? als off 10 ? 0 5v 30 50
rev. 1.00 18 ??to?e? 01? ?01? rev. 1.00 19 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom symbol parameter test conditions min. typ. max. unit v dd conditions i stb stand ? y cu ?? ent (idle0 mode) 3v no load ? all pe ? iphe ? als off ? f sub on 3 5 a 5v 5 10 a stand ? y cu ?? ent (idle1 mode) 3v f sys =f hxt =8mhz on ? f sub on no load ? all pe ? iphe ? als off 0.5 1.0 ma 5v 1.0 ? .0 ma 3v f sys =f hxt =1 ? mhz on ? f sub on no load ? all pe ? iphe ? als off 0.6 1. ? ma 5v 1. ? ? . ? ma 5v f sys =f hxt =16mhz on ? f sub on no load ? all pe ? iphe ? als off ? .0 ? .0 ma 5v f sys =f hxt = ? 0mhz on ? f sub on no load ? all pe ? iphe ? als off ? .5 5.0 ma 3v f sys =f hirc =8mhz on ? f sub on no load ? all pe ? iphe ? als off 0.8 1.6 ma 5v 1.0 ? .0 ma 3v f sys =f hirc =1 ? mhz on ? f sub on no load ? all pe ? iphe ? als off 1. ? ? . ? ma 5v 1.5 3.0 ma 5v f sys =f hirc =16mhz on ? f sub on no load ? all pe ? iphe ? als off ? .0 ? .0 ma stand ? y cu ?? ent (sleep0 mode) 3v f sub off ? wdt disa ? le no load ? all pe ? iphe ? als off 1.0 a 5v ? .0 a stand ? y cu ?? ent (sleep1 mode) 3v f sub on ? wdt ena ? le no load ? all pe ? iphe ? als off 3.0 a 5v 5.0 a v il input low voltage fo ? i/ ? po ? ts o ? input pins 5v 0 1.5 v 0 0. ? v dd v v ih input high voltage fo ? i/ ? po ? ts o ? input pins 5v 3.5 5.0 v 0.8v dd v dd v i ? l sink cu ?? ent fo ? i/ ? po ? t 3v v ? l = 0.1v dd 16 3 ? ma 5v v ? l = 0.1v dd 3 ? 6 ? ma i ? h sou ?? e cu ?? ent fo ? i/ ? po ? t 3v v ? h = 0.9v dd ? sledcn [m+1 ? m] = 00 n = 0 o ? 1; m = 0 ? ?? ? o ? 6 -1.0 - ? .0 ma 5v - ? .0 - ? .0 ma 3v v ? h = 0.9v dd ? sledcn [m+1 ? m] = 01 n = 0 o ? 1; m = 0 ? ?? ? o ? 6 -1.75 -3.5 ma 5v -3.5 -7.0 ma 5v v ? h = 0.9v dd ? sledcn [m+1 ? m] = 10 n = 0 o ? 1; m = 0 ? ?? ? o ? 6 - ? .5 -5.0 ma 3v -5.0 -10.0 ma 3v v ? h = 0.9v dd ? sledcn [m+1 ? m] = 11 n = 0 o ? 1; m = 0 ? ?? ? o ? 6 -5.5 -11.0 ma 5v -11.0 - ?? .0 ma r ph pull-high resistan ? e fo ? i/ ? po ? t s 3v ? 0 60 100 k 5v 10 30 50 k
rev. 1.00 ? 0 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 ?1 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom a.c. characteristics ta= ? 5c symbol parameter test condition min. typ. max. unit v dd condition f sys system clo ? k (hxt) ? . ? ~5.5v f sys =f hxt =8mhz 8 mhz ? .7~5.5v f sys =f hxt =1 ? mhz 1 ? mhz ? .5~5.5v f sys =f hxt =16mhz 16 mhz ? .5~5.5v f sys =f hxt = ? 0mhz ? 0 mhz system clo ? k (hirc) ? . ? ~5.5v f sys =f hirc =8mhz 8 mhz ? .7~5.5v f sys =f hirc =1 ? mhz 1 ? mhz ? .5~5.5v f sys =f hirc =16mhz 16 mhz system clo ? k (lxt) ? . ? ~5.5v f sys =f lxt =3 ? .768khz 3 ? .768 khz system clo ? k (lirc) ? . ? ~5.5v f sys =f lirc =3 ? khz 3 ? khz f lirc low speed inte ? nal rc os ? illato ? (lirc) 5v ta = ? 5c typ. -10% 3 ? typ. +10% khz ? . ? v~5.5v ta = - ? 0c to 85c typ. -50% 3 ? typ. +60% khz t tck tckn pin minimum input pulse width 0.3 s t int inte ?? upt pin minimum input pulse width 10 s t sst system sta ? t-up time ? pe ? iod (wake-up f ? om powe ? down mode and f sys off) f sys = f hxt off 1 ? 8 t hxt f sys = f hirc off 16 t hirc f sys = f lxt off 1 ? 8 t lxt f sys = f lirc off ? t lirc system sta ? t-up time ? pe ? iod (wake-up f ? om powe ? down mode) f sys on ? t sys t rstd system ? eset delay time (powe ? -on ? eset ? lvr ha ? dwa ? e ? eset ? lvrc/wdtc softwa ? e ? eset) ? 5 50 100 ms system ? eset delay time (wdt ha ? dwa ? e ? eset) 8.3 16.7 33.3 ms t eerd eepr ? m read time ? t sys t eewr eepr ? m w ? ite time ? ? ms 1rwh w sys i sys
rev. 1.00 ?0 ??to?e? 01? ?01? rev. 1.00 ? 1 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom hirc electrical characteristics ta= ? 5c frequency accuracy trimmed 8mhz at v dd =3v symbol parameter test conditions min. typ. max. unit v dd conditions f hirc high speed inte ? nal rc os ? illato ? (hirc) 3v ta = ? 5c typ. - ? % 8 typ. + ? % mhz 3v 0.3v ta = 0c ~ 70c typ. - 5% 8 typ. + 5% mhz 3v 0.3v ta = - ? 0c ~ 85c typ. - 7% 8 typ. + 7% mhz ? . ? v ~ 5.5v ta = 0c ~ 70c typ. - 7% 8 typ. + 7% mhz ? . ? v ~ 5.5v ta = - ? 0c ~ 85c typ. - 10% 8 typ. + 10% mhz 3v ta = ? 5c typ. - ? 0% 1 ? typ. + ? 0% mhz 3v ta = ? 5c typ. - ? 0% 16 typ. + ? 0% mhz frequency accuracy trimmed 8mhz at v dd =5v symbol parameter test conditions min. typ. max. unit v dd conditions f hirc high speed inte ? nal rc os ? illato ? (hirc) 5v ta = ? 5c typ. - ? % 8 typ. + ? % mhz 5v 0.5v ta = 0c ~ 70c typ. - 5% 8 typ. + 5% mhz 5v 0.5v ta = - ? 0c ~ 85c typ. - 7% 8 typ. + 7% mhz ? . ? v ~ 5.5v ta = 0c ~ 70c typ. - 7% 8 typ. + 7% mhz ? . ? v ~ 5.5v ta = - ? 0c ~ 85c typ. - 10% 8 typ. + 10% mhz 5v ta = ? 5c typ. - ? 0% 1 ? typ. + ? 0% mhz 5v ta = ? 5c typ. - ? 0% 16 typ. + ? 0% mhz frequency accuracy trimmed 12mhz at v dd =3v symbol parameter test conditions min. typ. max. unit v dd conditions f hirc high speed inte ? nal rc os ? illato ? (hirc) 3v ta = ? 5c typ. - ? % 1 ? typ. + ? % mhz 3v 0.3v ta = 0c ~ 70c typ. - 5% 1 ? typ. + 5% mhz 3v 0.3v ta = - ? 0c ~ 85c typ. - 7% 1 ? typ. + 7% mhz ? . ? v ~ 5.5v ta = 0c ~ 70c typ. - 7% 1 ? typ. + 7% mhz ? . ? v ~ 5.5v ta = - ? 0c ~ 85c typ. - 10% 1 ? typ. + 10% mhz 3v ta = ? 5c typ. - ? 0% 8 typ. + ? 0% mhz 3v ta = ? 5c typ. - ? 0% 16 typ. + ? 0% mhz
rev. 1.00 ?? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 ?3 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom frequency accuracy trimmed 12mhz at v dd =5v symbol parameter test conditions min. typ. max. unit v dd conditions f hirc high speed inte ? nal rc os ? illato ? (hirc) 5v ta = ? 5c typ. - ? % 1 ? typ. + ? % mhz 5v 0.5v ta = 0c ~ 70c typ. - 5% 1 ? typ. + 5% mhz 5v 0.5v ta = - ? 0c ~ 85c typ. - 7% 1 ? typ. + 7% mhz ? . ? v ~ 5.5v ta = 0c ~ 70c typ. - 7% 1 ? typ. + 7% mhz ? . ? v ~ 5.5v ta = - ? 0c ~ 85c typ. - 10% 1 ? typ. + 10% mhz 5v ta = ? 5c typ. - ? 0% 8 typ. + ? 0% mhz 5v ta = ? 5c typ. - ? 0% 16 typ. + ? 0% mhz frequency accuracy trimmed 16mhz at v dd =5v symbol parameter test conditions min. typ. max. unit v dd conditions f hirc high speed inte ? nal rc os ? illato ? (hirc) 5v ta = ? 5c typ. - ? % 16 typ. + ? % mhz 5v 0.5v ta = 0c ~ 70c typ. - 5% 16 typ. + 5% mhz 5v 0.5v ta = - ? 0c ~ 85c typ. - 7% 16 typ. + 7% mhz ? . ? v ~ 5.5v ta = 0c ~ 70c typ. - 7% 16 typ. + 7% mhz ? . ? v ~ 5.5v ta = - ? 0c ~ 85c typ. - 10% 16 typ. + 10% mhz 5v ta = ? 5c typ. - ? 0% 8 typ. + ? 0% mhz 5v ta = ? 5c typ. - ? 0% 1 ? typ. + ? 0% mhz a/d converter electrical characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v dd ? pe ? ating voltage ? .7 5.5 v v adi input voltage 0 v r\ef v v ref refe ? en ? e voltage ? v dd v dnl diffe ? ential non-linea ? ity 3v v ref =v dd ? t adck =0.5s 3 lsb 5v inl integ ? al non-linea ? ity 3v v ref =v dd ? t adck =0.5s ? lsb 5v i adc additional cu ?? ent consumption fo ? a/d conve ? te ? ena ? le 3v no load ? t adck =0.5s 1.0 ? .0 ma 5v 1.5 3.0 ma t adck clo ? k pe ? iod 0.5 10 s t adc conve ? sion time (a/d sample and hold time) 16 t adck t ? n ? st a/d conve ? te ? ? n-to-sta ? t time ? s
rev. 1.00 ?? ??to?e? 01? ?01? rev. 1.00 ? 3 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom lvd/lvr electrical characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v lvr low voltage reset voltage lvr ena ? le ? voltage sele ? t ? .1v typ. - 5% ? .1 typ. + 5% v lvr ena ? le ? voltage sele ? t ? .55v ? .55 lvr ena ? le ? voltage sele ? t 3.15v 3.15 lvr ena ? le ? voltage sele ? t 3.8v 3.8 v lvd low voltage dete ? to ? voltage lvd ena ? le ? voltage sele ? t ? .0v typ. - 5% ? .0 typ. + 5% v lvd ena ? le ? voltage sele ? t ? . ? v ? . ? lvd ena ? le ? voltage sele ? t ? . ? v ? . ? lvd ena ? le ? voltage sele ? t ? .7v ? .7 lvd ena ? le ? voltage sele ? t 3.0v 3.0 lvd ena ? le ? voltage sele ? t 3.3v 3.3 lvd ena ? le ? voltage sele ? t 3.6v 3.6 lvd ena ? le ? voltage sele ? t ? .0v ? .0 v bg bandgap refe ? en ? e voltage typ. - 3% 1.0 ? typ. + 3% v i ? p ? pe ? ating cu ?? ent 5v lvd/lvr ena ? le ? vbgen=0 ? 0 ? 5 a 5v lvd/lvr ena ? le ? vbgen=1 180 ? 00 a t bgs v bg tu ? n on sta ? le time no load 150 s t lvds lvd ? sta ? le time fo ? lvr ena ? le ? vbgen=0 ? lvd off : on 15 s fo ? lvr disa ? le ? vbgen=0 ? lvd off : on 150 s t lvr minimum low voltage width to reset 1 ? 0 ?? 0 ? 80 s t lvd minimum low voltage width to inte ?? upt 60 1 ? 0 ?? 0 s comparator electrical characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v dd ? pe ? ating voltage ? . ? 5.5 v i cmp additional cu ?? ent consumption fo ? ? ompa ? ato ? ena ? le 3v 37 56 a 5v 130 ? 00 a v ? s input offset voltage 5v -10 10 mv v cm common mode voltage ? ange v ss v dd -1. ? v a ? l ? pen loop gain 5v 60 80 db v hys hyste ? esis 5v hyste ? esis fun ? tion disa ? led 0 0 5 mv hyste ? esis fun ? tion ena ? led ? 0 ? 0 60 mv t rp response time with 100mv ove ? f ? ive 370 560 ns
rev. 1.00 ?? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 ?5 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom software controlled lcd driver electrical characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions i bias bias ? u ?? ent 5v isel[1:0]=00 ? . ? 8.3 13 a isel[1:0]=01 8.3 16.7 ? 5 a isel[1:0]=10 ? 5 50 75 a isel[1:0]=11 50 100 150 a v lcd_h [( ? /3) v dd ] voltage fo ? lcd sc ? m/sseg output ? . ? v~5.5v no load 0.6 ? 5 0.67 0.698 v dd v lcd_l [(1/3) v dd ] voltage fo ? lcd sc ? m/sseg output ? . ? v~5.5v no load 0.305 0.33 0.355 v dd power-on reset characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v p ? r v dd sta ? t voltage to ensu ? e powe ? -on reset 100 mv rr vdd v dd raising rate to ensu ? e powe ? -on reset 0.035 v/ms t p ? r minimum time fo ? v dd stays at v p ? r to ensu ? e powe ? -on reset 1 ms
rev. 1.00 ?? ??to?e? 01? ?01? rev. 1.00 ? 5 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom system architecture a key factor in the high-performan ce features of the holtek range of microcontrollers is attributed to their internal system architecture. the range of devices take advantag e of the usual features found within ris c microcontrollers providing increas ed s peed of operation and enhanced performance. the pi pelining sc heme i s i mplemented i n suc h a wa y t hat i nstruction fe tching a nd i nstruction execution a re ove rlapped, he nce i nstructions a re e ffectively e xecuted i n one c ycle, wi th t he exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithm etic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addresse d. the simple addressi ng met hods of these registers along with additi onal architectural features ensure that a minimum of external components is required to provide a functional i/ o a nd a/ d c ontrol syst em wi th m aximum re liability a nd fe xibility. t his m akes t hese devices suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a hxt , lxt , hirc or lirc oscillator is subdivided into four internall y generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are ef fectively executed in one instruction cycle. the exce ption to this are instructions where the content s of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute.
? ? ? ? ? ? ? ? system clocking and pipelining
rev. 1.00 ? 6 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 ?7 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into accou nt by programmers in timing sensitive applications.
? ? ? ? ? ? ? ? ? ? instruction fetching program counter during pro gram e xecution, t he progr am co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non- consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executi ng instructions re quiring jumps to non-consecutive addresses suc h as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. device program counter high byte low byte (pcl) HT66F0175 pc10~pc8 pc7~pc0 ht66f0185 pc11~pc8 pc7~pc0 program counter the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly; h owever, a s o nly t his l ow b yte is available for manipulation, the jumps are limited to the present page of memory that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.00 ?6 ??to?e? 01? ?01? rev. 1.00 ? 7 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has multiple levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allo wing the programmer to use the struct ure more easily . however , when the stack is full, a call subroutine instruction can still be execu ted which will result in a stack overfow . precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost. sta?k pointe? sta?k level ? sta?k level 1 sta?k level 3 : : : sta?k level 8 p?og?am memo?y p?og?am counte? bottom of sta?k top of sta?k arithmetic and logic unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation: rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement: inca, inc, deca, dec ? branch decision: jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.00 ? 8 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 ?9 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom flash program memory the program memory is the location where the user code or program is stored. for these devices series the program memory are flash type, which means it can be programmed and re-programmed a l arge num ber of t imes, a llowing t he use r t he c onvenience of c ode m odification on t he sa me device. by using the appropriate programming tools, these flash device s of fer users the fexibility to conveniently debug and develop their applications while also of fering a means of feld programming and updating. device capacity HT66F0175 ? k 16 ht66f0185 ? k 16 structure the program memory has a capaci ty of 2k16 to 4k16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. t able data, which c an b e se tup i n a ny l ocation wi thin t he pr ogram me mory, i s a ddressed b y a se parate t able pointer registers. 000h initialisation ve?to? 00?h fffh 16 ?its inte??upt ve?to?s 0??h look-up ta?le n00h nffh ht66f0185 initialisation ve?to? 16 ?its inte??upt ve?to?s look-up ta?le HT66F0175 0?8h 7ffh program memory structure special vectors within the program memory , certai n locations are reserved for the reset and interrupts. the location 000h is reserved for use by these devices reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution.
rev. 1.00 ?8 ??to?e? 01? ?01? rev. 1.00 ? 9 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register , tblp and tbhp . these registers defne the total address of the look-up table. after se tting u p t he t able p ointer, t he t able d ata c an b e r etrieved f rom t he pr ogram me mory u sing the t abrd [m] or t abrdl [m] instructions respectively . when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data me mory r egister [ m] a s sp ecified i n t he i nstruction. t he h igher o rder t able d ata b yte f rom the program memory will be transferred to the tblh special register . any unused bits in this transferred higher order byte will be read as 0. the accompanying diagram illustrates the addressing data fow of the look-up table.

table program example the accompanying example shows how the table pointer and table data is defned and retrieved from the devic e. this example uses raw table data located in the last page which is stored there using the org statement. the value at this org statement is 0f00h which refers to the start address of the last page within the 4k program memory of the device. the table pointer low byte register is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address 0f06h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page pointed by the tbhp register if the t abrd [m] instruction is being used. the high byte of the table data which in t his case i s equal t o z ero wi ll b e t ransferred t o t he t blh register a utomatically wh en t he tabrd [m] instruction is executed. because the tblh register is a read-only register and cannot be res tored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation.
rev. 1.00 30 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 31 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : mov a ,06h ; initialise low table pointer - note that this address is referenced mov t blp,a ; to the last page or the page that tbhp pointed mov a ,0fh ; initialise high table pointer mov tbhp,a : tabrd t empreg1 ; transfers value in table referenced by table pointer data at program ; memory address 0f06h transferred to tempreg1 and tblh dec t blp ; reduce value of table pointer by one tabrd t empreg2 ; transfers value in table referenced by table pointer data at program ; memory address 0f05h transferred to tempreg2 and tblh in this ; example the data 1ah is transferred to tempreg1 and data 0fh to ; register tempreg2 : org 0 f00h ; sets initial address of program memory dc 00 ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : in circuit programming C icp the p rovision o f fl ash t ype pr ogram me mory p rovides t he u ser wi th a m eans o f c onvenient a nd easy upgrades and modifcations to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in- circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming o r u pgrading t he p rogram a t a l ater st age. t his enables product m anufacturers to e asily keep thei r manufa ctured products supplied with the latest program releases without removal and re- insertion of the device. holtek writer pins mcu programming pins pin description icpda pa0 p ? og ? amming se ? ial data/add ? ess icpck pa ? p ? og ? amming clo ? k vdd vdd powe ? supply vss vss g ? ound the program memory and eeprom data memory can be programmed serially in-circuit using this 4-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. t wo additional lines are required for the power supply . the technical details regarding the in-cir cuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. during the programming process, the user must take care of the icpda and icpck pins for data and clock programming purposes to ensure that no other outputs are connected to these two pins.
rev. 1.00 30 ??to?e? 01? ?01? rev. 1.00 31 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom
note: * may be resistor or capacitor . the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf. on-chip debug support C ocds there is an ev chip named ht66v01x5 which is used to emulate the real mcu device named ht66f01x5. the ev chip device also provides the on-chip debug function to debug the real mcu device during development process. the ev chip and real mcu devices, ht66v01x5 and ht66f01x5, are almost functional compatible except the on-chip debug function. users can use the ev chip device to emulate the real m cu device behaviors by connecting the o cdsda and ocdsck pins to the holtek ht -ide development tools. the ocdsda pin is the ocds data/address input/ output pin whi le the ocdsck pin is the ocds clock input pin. when use rs use the ev chip device for debugging, the corresponding pin functions shared with the ocdsda and ocdsck pins in the real mcu device will have no ef fect in the ev chip. however , the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp . for more detailed ocds information, refer to the corresponding document named holtek e-link for 8-bit mcu ocds users guide. holtek e-link pins ev chip ocds pins pin description ? cdsda ? cdsda ? n-chip de ? ug suppo ? t data/add ? ess input/output ? cdsck ? cdsck ? n-chip de ? ug suppo ? t clo ? k input vdd vdd powe ? supply vss vss g ? ound
rev. 1.00 3 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 33 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom data memory the dat a mem ory is an 8-bit wide ram inte rnal me mory and is the loca tion where te mporary information is stored. structure divided into two banks, the frst of these is an area of ram, known as the special function data memory. he re a re l ocated r egisters wh ich a re n ecessary f or c orrect o peration o f t he d evice. ma ny of these registers can be read from and written to directly under program control, however , some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory , which is reserved for general purpose use. all locations within this area are read and write accessible under program control. the overall data memory is subdivided into two banks. the special purpose data memory registers are accessible in all banks, with the exception of the eec register at address 40h, which is only accessible in bank 1. switching between the dif ferent data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for the device is the address 00h. the address range of the special purpose data memory for the device is from 00h to 7fh while the address range of the general purpose data memory is from 80h to ffh. device capacity banks HT66F0175 1 ? 8 8 0: 80h~ffh ht66f0185 ? 56 8 0: 80h~ffh 1: 80h~ffh data memory summary 00h 7fh 80h ffh spe?ial pu?pose data memo?y gene?al pu?pose data memo?y bank 0 ?0h: eec HT66F0175 (bank 1) 00h 7fh 80h ffh spe?ial pu?pose data memo?y gene?al pu?pose data memo?y bank 0 bank 1 ?0h:eec (bank 1) ht66f0185 data memory structure
rev. 1.00 3? ??to?e? 01? ?01? rev. 1.00 33 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom 00h iar 0 01h mp 0 0?h iar 1 03h mp 1 0?h 05h acc 06h pcl 07h tblp 08h tblh 09h tbhp 0 ah status 0 bh 0 ch 0 dh 0 eh 0 fh 10h intc 0 11h 1?h 19h papu 18h pawu 1 bh 1 ah 1 dh 1 ch 1 fh pa pac 13h 1?h 15h 16h 17h eea ?0h ?1h ??h ?8h ?3h ??h ?5h ?6h ?7h ?0h ?1h ??h ?3h ??h ?5h ?6h ?7h ?8h ?9h ? ah ? bh ? ch ? dh ? eh ? fh 50h 51h 1 eh eec bank 0 ? 1 pbc pbpu pb 7 fh bp lvdc lvrc eed sad?l sadc 0 pcc pcpu pc sad?h 5?h sm?d integ intc 1 intc ? mfi 0 mfi 1 mfi ? tmpc wdtc tbc ctrl sadc 1 sadc ? bank 0 bank 1 sledc 0 sledc 1 acerl simt?c simc 0 simc 1 simd sima / simc ? slcdc 0 slcdc 1 slcdc ? slcdc 3 ifs ? eh 38 h 37 h 39 h 3 ah 3 ch 3 bh 3 dh 3 fh 3 eh tm 1c0 tm 1c1 tm 1 dl tm 1 dh tm 1 al tm 1 ah tm 1 rpl tm 1 rph ? fh 30h 31h 3?h 33h 3?h 35h ht 66 f 0175 tm 0c0 tm 0c1 tm 0 dl tm 0 dh tm 0 al tm 0 ah tm 0 rpl tm 0 rph : unused ? ?ead as 00h 36h 00 h iar 0 01 h mp 0 0? h iar 1 03 h mp 1 0? h 05 h acc 06 h pcl 07 h tblp 08 h tblh 09 h tbhp 0 ah status 0 bh 0 ch 0 dh 0 eh 0 fh 10 h intc 0 11 h 1? h 19 h papu 18 h pawu 1 bh 1 ah 1 dh 1 ch 1 fh pa pac 13 h 1? h 15 h 16 h 17 h eea ?0 h ?1 h ?? h ?8 h ?3 h ?? h ?5 h ?6 h ?7 h ?0 h ?1 h ?? h ?3 h ?? h ?5 h ?6 h ?7 h ?8 h ?9 h ? ah ? bh ? ch ? dh ? eh ? fh 50 h 51 h 53 h 5? h 1 eh eec bank 0 ? 1 55 h 56 h pbc pbpu pb 7 fh bp lvdc lvrc eed sad?l sadc 0 pcc pcpu pc 57 h 58 h 59 h 5 ah sad?h 5? h sm?d integ intc 1 intc ? mfi 0 mfi 1 mfi ? tmpc wdtc tbc ctrl sadc 1 sadc ? bank 0 bank 1 sledc 0 usr ucr1 ucr? txr _ rxr brg sledc 1 acerl simt?c simc 0 simc 1 simd sima / simc ? slcdc 0 slcdc 1 slcdc ? slcdc 3 ifs slcdc ? pd pdc pdpu tm ?c0 tm ?c1 tm ? dl tm ? dh tm ? al tm ? ah tm ? rp ?9 h ? ah ? bh ? ch ? dh ? eh 38h 37h 39h 3 ah 3 ch 3 bh 3 dh 3 fh 3 eh tm 1c0 tm 1c1 tm 1 dl tm 1 dh tm 1 al tm 1 ah tm 1 rpl tm 1 rph cpc ? fh 30 h 31 h 3? h 33 h 3? h 35 h ht 66f 0185 tm 0c0 tm 0c1 tm 0 dl tm 0 dh tm 0 al tm 0 ah tm 0 rp : unused ? ?ead as 00 h 36 h speciap purpose data memory structure
rev. 1.00 3 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 35 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom special function register description most of the special function register details will be described in the relevant functional section. however, several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operatio n to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair , iar0 and mp0 can together access data only from bank 0 while the iar1 register together with mp1 regist er pair ca n ac cess data from any dat a mem ory bank. as the indi rect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 the me mory po inters, k nown a s mp0 a nd mp1 , a re p rovided. t hese me mory po inters a re physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the releva nt indirect addressing registers is carried out, the actual address that the microcontroller is di rected to is the address specifed by the relat ed memory pointer . mp0, together with indirect addressing register , iar0, are used to access data from bank 0, while mp1 together with iar1 are used to access data from all data banks according to the corresponding bp register. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with frst ram address mov mp0,a ; setup memory pointer with frst ram address loop: clr iar0 ; clear the data at address defned by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: : the important point to note here is that in the example shown above, no reference is made to specifc ram addresses.
rev. 1.00 3? ??to?e? 01? ?01? rev. 1.00 35 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom bank pointer C bp for t he ht 66f0185 de vice, t he da ta me mory i s di vided i nto t wo ba nks, ba nk0 and ba nk1. selecting the required data memory area is achieved using the bank pointer . bit 0 of the bank pointer is used to select data memory banks 0~1. the data memory is initialised to bank 0 after a reset, except for a wdt time-out reset in the power down mode, in which case, the data memory bank remains unaf fected. it should be noted that the special function data memory is not af fected by t he ba nk se lection, whi ch m eans t hat t he spe cial func tion re gisters c an be a ccessed from within any bank. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer . accessing data from bank1 must be implemented using indirect addressing. bp register C ht66f0185 bit 7 6 5 4 3 2 1 0 name dmbp0 r/w r/w p ? r 0 bit 7~1 unimplemented, read as 0 bit 0 dmbp0 : select data memory banks 0: bank 0 1: bank 1 accumulator C acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user defi ned regi ster and anot her, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to control operation of the look-up table which is stored i n t he progra m me mory. t blp a nd t bhp a re t he t able poi nter a nd i ndicates t he l ocation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location.
rev. 1.00 36 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 37 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the clr wdt or hal t instruction. the pdf fag is af fected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac, and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also af fected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power -up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cle ared by a system power -up or executing the clr wdt or hal t instruction. to is set by a wdt time-out. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.
rev. 1.00 36 ??to?e? 01? ?01? rev. 1.00 37 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom status register bit 7 6 5 4 3 2 1 0 name t ? pdf ? v z ac c r/w r r r/w r/w r/w r/w p ? r 0 0 x x x x x: unknown bit 7~6 unimplemented, read as 0 bit 5 to : w atchdog t ime-out fag 0: after power up ow executing the clr wdt or halt instruction 1: a watchdog time-out occurred bit 4 pdf : power down fag 0: after power up ow executing the clr wdt instruction 1: by executing the halt instructin bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles, in addition, or no borrow from the high nibble into the low nibble in substraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation the c fag is also affected by a rotate through carry instruction.
rev. 1.00 38 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 39 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom eeprom data memory these d evices c ontain a n a rea o f i nternal e eprom da ta me mory. e eprom, wh ich st ands f or electrically e rasable progra mmable re ad onl y me mory, i s by i ts na ture a non-vol atile form of re-programmable memory , with data retention even when its power supply is removed. by incorporating this kind of data memory , a w hole new hos t of application pos sibilities are made available to the designer . the avail ability of eeprom storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the e eprom da ta me mory c apacity i s up t o 12 88 bi ts for t he se ries of de vices. unl ike t he program memory and ram data memory , the eeprom data memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. read and w rite operations to the eeprom are carried out in single byte operations using an address and data register in bank 0 and a single control register in bank 1. device capacity address HT66F0175 6 ? 8 00h ~ 3fh ht66f0185 1 ? 8 8 00h ~ 7fh eeprom registers three registers control the overall operation of the internal eeprom data memory . these are the address register , eea, the data register , eed and a single control register , eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same was as any other special function register . the eec register , however , being located in bank 1, can be read from or written to indirectly using the mp1 memory pointer and indirect address ing regis ter, iar1. because the ee c control regist er is loca ted at addre ss 40h in bank 1, the mp1mem ory point er register must frst be set to the value 40h and the bank pointer register , bp , set to the value, 01h, before any operations on the eec register are executed. register name bit 7 6 5 4 3 2 1 0 eea (HT66F0175) eea5 eea ? eea3 eea ? eea1 eea0 eea (ht66f0185) eea6 eea5 eea ? eea3 eea ? eea1 eea0 eed d7 d6 d5 d ? d3 d ? d1 d0 eec wren wr rden rd eeprom registers list eea register C HT66F0175 bit 7 6 5 4 3 2 1 0 name eea5 eea ? eea3 eea ? eea1 eea0 r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~0 eea5~eea0 : data eeprom address bit 5 ~ bit0
rev. 1.00 38 ??to?e? 01? ?01? rev. 1.00 39 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom eea register C ht66f0185 bit 7 6 5 4 3 2 1 0 name eea6 eea5 eea ? eea3 eea ? eea1 eea0 r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6~0 eea6~eea0 : data eeprom address bit 6 ~ bit0 eed register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : data eeprom data bit 7~bit0 eec register bit 7 6 5 4 3 2 1 0 name wren wr rden rd r/w r/w r/w r/w r/w p ? r 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3 wren : data eeprom write enable 0: disable 1: enable this is the d ata eep rom w rite enable bit w hich mus t be s et high before d ata eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr : eeprom write control 0: w rite cycle has fnished 1: activate a write cycle this i s t he da ta e eprom w rite c ontrol b it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no ef fect if the wren has not frst been set high. bit 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero w ill inhibit d ata eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set hi gh by the applic ation program will activ ate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no ef fect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to 1 at the same time in one instruction. the wr and rd can not be set to 1 at the same time.
rev. 1.00 ? 0 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 ?1 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom reading data from the eeprom to read data from the eep rom, the read enable bit, rden , in the eec register must frs t be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register . if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle term inates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register . the data will remain in the eed register until another read or write operation i s e xecuted. t he a pplication pr ogram c an po ll t he rd bi t t o de termine whe n t he da ta i s valid for reading. writing data to the eeprom to write data to the eeprom, the eeprom address of the data to be written must frst be placed in t he ee a regist er and t he dat a pla ced in t he ee d regist er. then t he writ e enabl e bit , wren, in the eec register must first be set high to enable the write function. after this, the wr bit in the e ec r egister m ust be i mmediately se t hi gh t o i nitiate a wri te c ycle. t hese t wo i nstructions must be executed consecutively . the global interrupt bit emi should also first be cleared before implementing any write operations, and then set again after the write cycle has started. note that setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller , informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered on, the w rite enable bit in the control regis ter w ill be cleared preventing any w rite operations. also at power -on the bank pointer register , bp , will be reset to zero, which means that data mem ory ba nk 0 wil l be sel ected. as t he e eprom c ontrol re gister i s l ocated i n ba nk 1, t his adds a f urther m easure o f p rotection a gainst sp urious wr ite o perations. du ring n ormal p rogram operation, ensuring that the w rite enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must frst be enabled by setting the dee bit in the relevant interrupt register . however , as the eeprom is contained within a multi-function interrupt, the associated multi-function interrupt enable bit must als o be set. when an eeprom w rite cycle ends, the d ef reques t flag and its associated multi-function interrupt request fag will both be set. if the global, eeprom and multi- function interrupts are enabled and the stack is not full, a jump to the associated multi-function interrupt vector will take place. when the interrupt is serviced only the multi-function interrupt fag will be automatically reset, the eeprom interrupt fag must be manually reset by the application program.
rev. 1.00 ?0 ??to?e? 01? ?01? rev. 1.00 ? 1 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be periodic by ensuring that the w rite enable bit is normally cleared to zero when not writing. also the bank pointer register could be normally cleared to zero as this would inhibit access to bank 1 where the eeprom control regis ter exis t. a lthough certainly not neces sary, cons ideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly . the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. note that the devic e should not enter the idle or sleep mode until the eeprom read or write operation is totally complete. otherwise, the eeprom read or write operation will fail. programming example reading data from the eeprom - polling method mov a , eeprom_adres ; user defned address mov e ea, a mov a , 040h ; setup memory pointer mp1 mov m p1, a ; mp1 points to eec register mov a , 01h ; setup bank pointer bp mov b p, a set i ar1.1 ; set rden bit, enable read operations set i ar1.0 ; start read cycle - set rd bit back: sz i ar1.0 ; check for read cycle end jmp b ack clr i ar1 ; disable eeprom write clr bp mov a , eed ; move read data to register mov r ead_data, a writing data to the eeprom - polling method mov a , eeprom_adres ; user defned address mov e ea, a mov a , eeprom_data ; user defned data mov e ed, a mov a , 040h ; setup memory pointer mp1 mov m p1, a ; mp1 points to eec register mov a , 01h ; setup bank pointer bp mov b p, a clr e mi set i ar1.3 ; set wren bit, enable write operations set i ar1.2 ; start write cycle - set wr bit set e mi back: sz i ar1.2 ; check for write cycle end jmp b ack clr i ar1 ; disable eeprom write clr bp
rev. 1.00 ?? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 ?3 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom oscillator various oscillator types offer the user a wide range of functions according to their various application requirements. the fexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options and relevant control registers. oscillator overview in additio n to being the source of the main system clock the oscillators also provide clock sources for t he w atchdog t imer a nd t ime b ase i nterrupts. e xternal o scillators r equiring so me e xternal components as well as fully integrated internal oscillators, requiring no external components, are provided t o fo rm a wi de ra nge of bo th fa st a nd sl ow syst em osc illators. al l osc illator op tions a re selected through confguration options. the higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. w ith the capability of dynamically switching between fast and slow system clock, the device has the fexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. type name frequency pins high speed exte ? nal c ? ystal hxt ? 00 khz~ ? 0 mhz ? sc1/ ? sc ? high speed inte ? nal rc hirc 8/1 ? /16 mhz low speed exte ? nal c ? ystal lxt 3 ? .768 khz xt1/xt ? low speed inte ? nal rc lirc 3 ? khz oscillator types system clock confgurations there are four methods of generating the system clock, two high speed oscillators for all devices and two low speed oscillators. the high speed oscillator is the external crystal/ceramic oscillator , hxt , and t he i nternal 8 /12/16 mhz r c o scillator, hi rc. t he t wo l ow sp eed o scillators a re t he i nternal 32 khz rc oscillator , lirc, and the external 32.768 khz crystal oscillator , lxt . selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2~cks0 bits in the smod register and as the system clock can be dynamically selected. the a ctual sourc e c lock use d for e ach of t he hi ogh a nd l ow spe ed osc illators i s c hosen vi a configuration options. the frequency of the slow speed or high speed system clock is also determined using the hlclk bit and cks2~cks0 bits in the smod register . note that two oscillator selection s must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator . the osc1 and osc2 pins are used to connect the external components for the external crystal.
rev. 1.00 ?? ??to?e? 01? ?01? rev. 1.00 ? 3 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom hirc p?es?ale? f h lxt high speed ?s?illation low speed ?s?illation f h /? f h /16 f h /6? f h /8 f h /? f h /3? hlclk? cks?~cks0 f sys f sub f sub lirc hxt f h high speed ?s?illato? configu?ation ?ption low speed ?s?illato? configu?ation ?ption fast wake-up f?om idle o? sleep mode cont?ol (fo? hxt only ) system clock confgurations external crystal/ceramic oscillator C hxt the e xternal cryst al/ceramic syst em osc illator i s one of t he hi gh fre quency osc illator c hoices, which is s elected via configuration option. f or mos t crystal os cillator configurations, the s imple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, without requiring extern al capacitors. however , for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected as shown for oscillation to occur . the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturers specifcation. for oscillator stability and to minimise the ef fects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the mcu as possible.
? ? ?? crystal/resonator oscillator hxt oscillator c1 and c2 values crystal frequency c1 c2 1 ? mhz 0 pf 0 pf 8mhz 0 pf 0 pf ? mhz 0 pf 0 pf 1mhz 100 pf 100 pf note: c1 and c ? values a ? e fo ? guidan ? e only. crystal recommended capacitor values
rev. 1.00 ?? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 ?5 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom internal high speed rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the inter nal rc oscillator has three fxed frequencies of 8mhz, 12mhz, 16mhz. device trimming during the manufa cturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperat ure and process variations on the oscillation frequency are minimised. as a result, at a power supply of either 3v or 5v and at a temperature of 25c degrees, the fxed oscillation frequency of 8mhz, 12mhz or 16mhz will have a tolerance within 2%. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins are free for use as normal i/o pins. the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has a fixed frequency of 8/12/16 mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensati on circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25c degrees, the fxed oscillation frequency of 8mhz, 12mhz or 16mhz will have a tolerance within 2%. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins are free for use as normal i/o pins. external 32.768 khz crystal oscillator C lxt the external 32.768khz crystal system oscillator is one of the low frequency oscillator choices, which i s se lected v ia c onfguration o ption. t his c lock so urce h as a fx ed f requency o f 3 2.768 k hz and requires a 32.768 khz crystal to be connected between pins xt1 and xt2. the external resistor and capacitor components connected to the 32.768 khz crystal are necessary to provide oscillation. for a pplications wh ere p recise f requencies a re e ssential, t hese c omponents m ay b e r equired t o provide frequency compensation due to dif ferent crystal manufacturing tolerances. during power -up there is a time delay associated with the lxt oscillator waiting for it to start-up. when the microco ntroller enters the sleep or idle mode, the system clock is switched of f to stop microcontroller a ctivity a nd t o c onserve powe r. howe ver, i n m any m icrocontroller a pplications it may be necessary to keep the internal timers operational even when the microcontroller is in the sleep or idle mode. t o do this, another clock, independent of the system clock, must be provided. however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer specification. the external parallel feedback resistor, rp, is required. some confguration options determine if the xt1/xt2 pins are used for the lxt oscillator or as i/o or other pin-shared functional pins. ? if the lxt oscilla tor is not used for any clock source, the xt1/xt2 pins can be used as normal i/ o or other pin-shared functional pins. ? if the lxt oscilla tor is used for any clock source, the 32.768 khz crystal should be connected to the xt1/xt2 pins. for oscillator stability and to minimise the ef fects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the mcu as possible.
rev. 1.00 ?? ??to?e? 01? ?01? rev. 1.00 ? 5 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom
? ? ? ? ? ?- ? ? ? external lxt oscillator lxt oscillator c1 and c2 values crystal frequency c1 c2 3 ? .768 khz 10 pf 10 pf note : 1. c1 and c ? values a ? e fo ? guidan ? e only. ? . r p =5m~10m is recommended. 32.768 khzcrystal recommended capacitor values lxt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the lxtlp bit in the tbc register. lxtlp lxt operating mode 0 qui ? k sta ? t 1 low-powe ? after power on, the lxtlp bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly . however , after the lxt oscillator has fully powered up it can be placed into t he l ow-power m ode b y se tting t he l xtlp b it h igh. t he o scillator wi ll c ontinue t o r un b ut with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets t he l xtlp bi t hi gh a bout 2 se conds a fter powe r-on. it shoul d be not ed t hat, no m atter wha t condition t he l xtlp bi t i s se t t o, t he l xt osc illator wi ll a lways func tion norm ally a nd t he onl y difference is that it will take more time to start up if in the low-power mode. internal 32khz oscillator C lirc the internal 32khz system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. it is a fully integrated rc oscillator with a typical frequency of 32 khz at 5v , requiring no ext ernal com ponents for it s im plementation. devi ce tri mming duri ng the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25c degrees, the fxed oscillation frequency of 32 khz will have a tolerance within 10%. supplementary oscillators the l ow spe ed osc illators, i n a ddition t o pro viding a syst em c lock sour ce a re a lso use d t o pro vide a c lock so urce t o t wo o ther d evice f unctions. t hese a re t he w atchdog t imer a nd t he t ime b ase interrupts.
rev. 1.00 ? 6 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 ?7 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom operating modes and system clocks present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red port able a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. as holtek has provided the device with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the device has many dif ferent clock sources for both the cpu and peripheral function operation. by providing the us er w ith a w ide range of clock options us ing conf guration options and regis ter programming, a clock system can be confgured to obtain maximum application performance. the main system clock, can come from either a high frequency f h or low frequency f sub source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register. the high speed system clock can be sourced from either an hxt or hirc oscillator , selected via a confguration option. the low speed system clock source can be sourced from internal clock f sub . if f sub is selected then it can be sourced by either the lxt or lirc oscillator , selected via a confguration option. the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~ f h /64. there are two additional internal clocks for the peripheral circuits, the substitute clock, f sub , and the t ime base clock, f tbc . each of these internal clocks is sourced by either the lxt or lirc oscillators, selected via confguration options. the f sub clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times. hirc p?es?ale? f h lxt high speed ?s?illation low speed ?s?illation f h /? f h /16 f h /6? f h /8 f h /? f h /3? hlclk? cks?~cks0 f sys f sub f sub lirc hxt f h high speed ?s?illato? configu?ation ?ption low speed ?s?illato? configu?ation ?ption fast wake-up f?om idle o? sleep mode cont?ol (fo? hxt only ) f sub idlen f tbc f sys /? tbck f tb time base wdt f sub f tbc device clock confgurations note: when the system clock source f sys is switched to f sub from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use.
rev. 1.00 ?6 ??to?e? 01? ?01? rev. 1.00 ? 7 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom system operation modes there are six dif ferent modes of operation for the microcontroller , each one with its ow n special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. there are two modes all owing normal operati on of the microcontroller, t he normal mode a nd sl ow mode . t he re maining four m odes, t he sl eep0, sleep1, idle0 and idle1 mode, are used when the microcontroller cpu is switched of f to conserve power. operation mode description cpu f sys f sub f tbc n ? rmal ? n f h ~f h /6 ? ? n ? n sl ? w ? n f sub ? n ? n idle0 ? ff ? ff ? n ? n idle1 ? ff ? n ? n ? n sleep0 ? ff ? ff ? ff ? ff sleep1 ? ff ? ff ? n ? ff normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. this mode operate s allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the hxt or hirc oscillators. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod register . although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally altho ugh now with a slower speed clock source. the clock source used will be from one of the low speed oscillators, either the lxt or the lirc. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep0 mode the sleep0 mode is entered when an hal t instruction is executed and when the idlen bit in the smod registe r is low . in the sleep0 mode the cpu will be stopped, the f sub clock will also be stopped and the w atchdog t imer function is disabled. in this mode, the l vden must be set to 0. if the lvden is set to 1, it wont enter the sleep0 mode. sleep1 mode the sleep1 mode is entered when an hal t instruction is executed and when the idlen bit in the smod register is low . in the sleep1 mode the cpu will be stopped. however the f sub clock will continue to operate if the w atchdog t imer function is enabled. idle0 mode the idle0 mode is entered when a hal t instruction is executed and when the idlen bit in the smod regi ster i s high and t he fsyson bit i n t he ctrl regi ster i s l ow. in t he idle 0 mode t he system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational such as the watchdog timer and tms. in the idle0 mode, the system oscillator will be stopped.
rev. 1.00 ? 8 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 ?9 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom idle1 mode the idle1 mode is entered when an hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational such as the w atchdog t imer and tms. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. control registers a single register, smod, is used for overall control of the internal clocks within the devices. smod register bit 7 6 5 4 3 2 1 0 name cks ? cks1 cks0 fsten lt ? ht ? idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w p ? r 0 0 0 0 0 0 1 1 bit 7~5 cks2~cks0 : system clock selection when hlclk is 0 000: f 001: f 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be either the lxt or lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 fsten : fast w ake-up control (only for hxt) 0: disable 1: enable this i s t he fa st w ake-up c ontrol b it wh ich d etermines i f t he f c lock so urce i s initially used after the device wakes up. when the bit is high, the f clock source can be used as a temp orary system clock to provide a faster wake up time as the f clock is available. bit 3 lto : low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscilla tor ready fag which indicates when the low speed system oscillator is stable after pow er on reset or a wake-up has occurred. the fag will be low when in the sleep0 mode but after a wake-up has occurred, the fag will change to a high level after 128 clock cycles if the lxt oscillator is used and 1~2 clock cycles if the lirc oscillator is used.
rev. 1.00 ?8 ??to?e? 01? ?01? rev. 1.00 ? 9 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom bit 2 hto : high speed system oscillator ready fag 0: not ready 1: ready this is the high speed system oscillator ready fag which indicates when the high speed system oscillator is stable. this fag is cleared to 0 by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this fag will always be read as 1 by the application program after device power-on. the fag will be low when in the sleep or idle0 mode but after a wake- up has occurred, the fag will change to a high level after 512 clock cycles if the hxt oscillator is used and after 15~16 clock cycles if the hirc oscillator is used. bit 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the ha lt instruction is executed. if this bit is high, when a hal t instruction is execured, the device wi ll e nter t he idl e m ode. in t he idl e m ode t he c pu wi ll st op ru nning bu t the system clock will continye to keep the peripheral functions operational, if the fsyson bit is high. if the fsyson bit is low , the cpu and the system clock will all stop in idle0 mode. if the bit is low , the device will enter the sleep mode when a halt instruction is executed. bit 0 hlclk : system clock selection 0: f h /2~f h /64 or f sub 1: f h this bit is used to select if the f h clock or the f h /2~f h /64 or f sub clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2~f h /64 or f sub clock will be selected. when system clock sw itches from the f h clock to the f sub clock and the f h clock will be automatically switched of f to conserve power. name fsys ? n lvrf lrf wrf r/w r/w r/w r/w r/w p ? r 0 x 0 0 x: unknown bit 7 fsyson : f sys control in idle mode 0: disable 1: enable this bit is used to control whether the system clock is switched on or not in the idle mode. if this bit is set to 0, the system clock will be switched of f in the idle mode. however, the system clock will be switched on in the idle mode when the fsyson bit is set to !. bit 6~3 unimplemented, read as 0 bit 2 lvrf : lvr function reset fag described elsewhere. bit 1 lrf : lvr control register software reset fag described elsewhere. bit 0 wrf : wdt control register software reset fag described elsewhere.
rev. 1.00 50 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 51 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom fast wake-up to minimise power consumption the device can enter the sleep or idle0 mode, where the system clock source to the device will be stopped. however when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to re sume. t o e nsure t he de vice i s up a nd runni ng a s fa st a s possi ble a fa st w ake-up func tion i s provided, which allows f sub , namel y either the lxt or lirc oscillator , to act as a temporary clock to frst drive the system until the original system oscillator has stabilised. as the clock source for the fast w ake-up function is f sub , the fast w ake-up function is only available in the sleep1 and idle0 modes. when the device is woken up from the sleep0 mode, the fast w ake-up function has no ef fect because the f sub clock is stopped. the fast w ake-up enable/ disable function is controlled using the fsten bit in the smod register. if the hxt oscil lator is sel ected as the normal mode syste m cl ock, and if the fa st w ake-up function is enabled, then it will take one to two tsub clock cycles of the lirc or lxt oscillator for the system to wake-up. the system will then initially run under the f sub clock source until 512 hxt clock cycles have elapsed, at which point the ht o fag will switch high and the system will switch over to operating from the hxt oscillator. if the hirc oscillator or lirc oscillator is used as the system oscillator then it will take 15~16 clock c ycles of t he hirc or 1~2 c ycles of t he l irc t o wa ke up t he syst em from t he sl eep or idle0 mode. the fast w ake-up bit, fsten will have no effect in these cases. system oscillator fsten bit wake-up time (sleep0 mode) wake-up time (sleep1 mode) wake-up time (idle0 mode) wake-up time (idle1 mode) hxt 0 1 ? 8 hxt ? y ? les 1 ? 8 hxt ? y ? les 1~ ? hxt ? y ? les 1 1 ? 8 hxt ? y ? les 1~ ? f sub ? y ? les (system ? uns with f sub fi ? st fo ? 51 ? hxt ? y ? les and t hen swit ? hes ove ? t o ? un with the hxt ? lo ? k) 1~ ? hxt ? y ? les hirc x 15~16 hirc ? y ? les 15~16 hirc ? y ? les 1~ ? hirc ? y ? les lirc x 1~ ? lirc ? y ? les 1~ ? lirc ? y ? les 1~ ? lirc ? y ? les lxt x 1 ? 8 hxt ? y ? les 1~ ? lxt ? y ? les 1~ ? lxt ? y ? les x: dont ? a ? e wake-up times note that if the w atchdog t imer is disabled, which means that the lxt and lirc are all both of f, then there will be no fast w ake-up function available when the device wake-up from the sleep0 mode.
rev. 1.00 50 ??to?e? 01? ?01? rev. 1.00 51 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom operating mode switching these devices can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the pres ent task in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the hal t instruction. when a hal t instruction is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smodregister and the fsyson bit in the ctrl register. normal f sys =f h ~f h /6? f h on cpu ?un f sys on f sub on f tbc on slow f sys =f sub f sub on cpu ?un f sys on f h off f tbc on idle0 halt inst?u?tion exe?uted cpu stop idlen=1 fsys?n=0 f sys off f sub on f tbc on idle1 halt inst?u?tion exe?uted cpu stop idlen=1 fsys?n=1 f sys on f sub on f tbc on sleep1 halt inst?u?tion exe?uted cpu stop idlen=0 f sys off f sub on f tbc off wdt on sleep0 halt inst?u?tion exe?uted cpu stop idlen=0 f sys off f sub off f tbc off wdt & lvd off when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock, f h , to the clock source, f h /2~f h /64 or f sub . if the clock is from the f sub , the high speed c lock so urce wi ll st op r unning t o c onserve p ower. w hen t his h appens, i t m ust b e n oted t hat the f h /16 and f h /64 internal clock sources will also stop running, which may af fect the operation of other internal functions such as the tm s. the accompamying chart s hows w hat happens w hen the device moves between the various operating modes.
rev. 1.00 5 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 53 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom normal mode to slow mode switching when running in the normal mode, which uses the high speed system oscillator , and therefore consumes more power, the system clock can switch to run in the slow mode by set the hlclk bit to 0 and set the cks2~cks0 bits to 000 or 001 in the smod register . this will then use the low speed system oscillator which will consume less power . users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lxt or lirc oscillator determined by the configuration option and therefo re requires this oscillator to be stable before full mode switching occurs. this is monitored using the lto bit in the smod register. normal mode slow mode cks?~cks0 = 00xb & hlclk = 0 sleep0 mode idlen=0 halt inst?u?tion is exe?uted sleep1 mode idle0 mode idle1 mode wdt and lvd a?e all off idlen=0 halt inst?u?tion is exe?uted wdt is on idlen=1? fsys?n=0 halt inst?u?tion is exe?uted idlen=1? fsys?n=1 halt inst?u?tion is exe?uted
rev. 1.00 5? ??to?e? 01? ?01? rev. 1.00 53 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom slow mode to normal mode switching in slow mode the system uses either the lxt or lirc low speed system oscillator . t o switch back to the narmal mode, where the high speed system oscillator is used, the hlclk bit should be set to 1 or hlclk bit is 0, but cks2~cks0 feld is set to 010, 011, 100, 101, 110 or 1 11. as a certain amount of tim e will be required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. normal mode slow mode cks2~cks0 000b or 001b as hlclk = 0 or hlclk = 1 sleep0 mode idlen=0 halt instruction is executed sleep1 mode idle0 mode idle1 mode wdt and lvd are all off idlen=0 halt instruction is executed wdt is on idlen=1, fsyson=0 halt instruction is executed idlen=1, fsyson=1 halt instruction is executed entering the sleep0 mode there is only one way for the devic e to enter the sleep0 mode and that is to execute the hal t instruction in the application program with the idlen bit in the smod register equal to 0 and the wdt and l vd both of f. when this instruction is executed under the conditions described above, the following will occur: ? the system clock, wdt clock and t ime base clock will be stopped and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the w dt wi ll be c leared a nd st opped no m atter i f t he w dt c lock sourc e or ginates from t he lxt or lirc oscillator. ? the i/o ports will maintain their present conditions. ? in t he st atus r egister, t he po wer do wn fa g pdf wi ll b e se t, a nd w dt t imeout fa g t o wi ll b e cleared.
rev. 1.00 5 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 55 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom entering the sleep1 mode there is only one way for the devic e to enter the sleep1 mode and that is to execute the hal t instruction in the application program with the idlen bit in the smod register equal to 0 and the wdt on. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and t ime base clock will be stopped and the application program will stop at the " halt" ins truction, but the wdt will remain with the clock source coming from the f sub clock. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt function is enabled. ? the i/o ports will maintain their present conditions. ? in t he st atus r egister, t he po wer do wn fa g pdf wi ll b e se t, a nd w dt t imeout fa g t o wi ll b e cleared. entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n t he smod r egister e qual t o 1 a nd the fsyson bit in the ctrl register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the hal t instruction, but the f tbc and f sub clocks will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt function is enabled. ? the i/o ports will maintain their present conditions. ? in t he st atus r egister, t he po wer do wn fa g pdf wi ll b e se t, a nd w dt t imeout fa g t o wi ll b e cleared. entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n t he smod r egister e qual t o 1 a nd the fsyson bit in the ctrl register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the system clock, f tbc and f sub clocks will be on but the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt function is enabled. ? the i/o ports will maintain their present conditions. ? in t he st atus r egister, t he po wer do wn fa g pdf wi ll b e se t, a nd w dt t imeout fa g t o wi ll b e cleared.
rev. 1.00 5? ??to?e? 01? ?01? rev. 1.00 55 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode , t here a re ot her c onsiderations whi ch m ust a lso be t aken i nto a ccount by t he c ircuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have dif ferent package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the lirc oscillator has enabled. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed oscillator, the additional standby current will also be perhaps in the order of several hundred micro- amps. wake-up to minimise power consumption the device can enter the sleep or any idle mode, where the cpu will be switched of f. however , when the device is woken up again, it will take a considerable time for the original system oscillator to restart, stablise and allow normal operation to resume. after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external falling edge on port a ? a system interrupt ? a wdt overfow when the device executes the hal t instruction, it will enter the power down mode and the pdf fag will be set to 1. the pdf fag will be cleared to 0 if the device experiences a system power -up or executes the cle ar w atchdog t imer instruction. if the system is woken up by a wdt overfow , a watchdog t imer reset will be initia ted and the t o fag will be set to 1. the t o fag is set if a wdt time-out occurs and causes a wake-up that only resets the program counter and stack pointer , other fags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake up the system . when a port a pin wake-up occurs, the program wil l resume executi on at the i nstruction f ollowing t he halt i nstruction. i f t he sy stem i s wo ken u p by a n i nterrupt, t hen two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the h alt ins truction. in this s ituation, the interrupt w hich w oke up the device w ill not be immediately serviced, but wukk rather be serviced later when the related interrupt is fnally enabled o r wh en a st ack l evel b ecomes f ree. t he o ther si tuation i s wh ere t he r elated i nterrupt i s enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request fag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled.
rev. 1.00 56 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 57 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom programming considerations the high speed and low speed oscillators both use the same sst counter . for example, if the system is woken up from the sleep0 mode and both the hirc and lxt oscillators need to start-up from an of f state. the lxt oscillator uses the sst counter after the hirc oscillator has fnished its sst period. ? if the device is woken up from the sleep0 mode to the normal mode, the high speed system oscillator needs an sst period. the device will execute frst instruction after ht o is 1. at this time, t he l xt o scillator m ay n ot b e st ability i f f sub i s f rom l xt o scillator. t he sa me si tuation occurs in the power -on state. the lxt oscillator is not ready yet when the frst instruction is executed. ? if the device is woken up from the sleep1 mode to normal mode, and the system clock source i s f rom t he hxt o scillator a nd fst en i s 1, t he sy stem c lock c an b e swi tched t o t he lirc oscillator after wake up. ? there are peripheral functions, such as wdt and tms, for which the f sys is used. if the system clock source is switched from f h to f sub , the clock source to the peripheral functions mentioned above will change accordingly. ? the on/of f conditi on of f sub and f s depends upon whether the wdt is enabled or disabled as the wdt clock source is selected from f sub . watchdog timer the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the w atchdog t imer clock source is provided by the internal clock, f sub , which is in turn supplied by t he l irc or l xt osc illator. t he l xt osc illator i s supp lied by a n e xternal 32 .768 khz c rystal. the lirc internal oscillator has an approximate frequency of 32 khz at a supply voltage of 5v. h owever, it s hould be noted that this s pecified internal clock frequency can vary w ith v dd , temperature and process variations. the w atchdog t imer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. watchdog timer control register a single register , wdtc, controls the required timeout period as well as the enable/disable operation. this register controls the overall operation of the w atchdog t imer.
rev. 1.00 56 ??to?e? 01? ?01? rev. 1.00 57 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom wdtc register bit 7 6 5 4 3 2 1 0 name we ? we3 we ? we1 we0 ws ? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 1 0 1 0 0 1 1 bit 7~3 we4~we0 : wdt function enable control 10101: disabled 01010: enabled other values: reset mcu if these bits are changed due to adverse environmental conditions, the microcontroller will be reset. the reset operation will be activated after 2~3 lirc clock cycles and the wrf bit in the ctrl register will be set to 1. bit 2~0 ws2~ws0 : wdt time-out period selection 000: 2 8 /f 001: 2 /f 010: 2 /f 011: 2 /f 100: 2 /f 101: 2 16 /f 110: 2 /f 111: 2 18 /f these t hree b its d etermine t he d ivision r atio o f t he wa tchdog t imer so urce c lock, which in turn determines the time-out period. ctrl register bit 7 6 5 4 3 2 1 0 name fsys ? n lvrf lrf wrf r/w r/w r/w r/w r/w p ? r 0 x 0 0 x: unknown bit 7 fsyson : f control in idle mode described elsewhere. bit 6~3 unimplemented, read as 0 bit 2 lvrf : lvr function reset fag described elsewhere. bit 1 lrf : lvr control register software reset fag described elsewhere. bit 0 wrf : wdt control register software reset fag 0: not occurred 1: occurred this bi t i s se t t o 1 by t he w dt c ontrol re gister soft ware re set a nd c leared by t he application pr ogram. not e t hat t his bi t c an on ly be c leared t o 0 by t he a pplication program.
rev. 1.00 58 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 59 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom watchdog timer operation the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the clear watchdog instruction. if the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, the clear instructio n will not be executed in the correct manner, in which case the w atchdog t imer will overfow and reset the device. w ith regard to the w atchdog t imer enable/disable function, there are fve bits, we4~we0, in the wdtc register to of fer the enable /disable control and reset control of the w atchdog t imer. the wdt function will be disa bled when the we 4~we0 bit s are se t to a val ue of 10101b whil e the wdt funct ion wi ll be enabled if the we4~we0 bits are equal to 01010b. if the we4~we0 bits are set to any other values, except 01010b and 10101b, it will reset the device after 2~3 f lirc clock cycles. after power on these bits will have a value of 01010b. we4 ~ we0 bits wdt function 10101b disa ? le 01010b ena ? le any othe ? value reset mcu watchdog timer enable/disable control under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the w atchdog t imer. the frst is a wdt reset, which means a certain value except 01010b and 10101b written into the we4~we0 feld, the second is using the w atchdog t imer software cle ar instruction and the third is via a halt instruction. there is only one method of using software instruction to clear the w atchdog t imer. that is to use the single clr wdt instruction to clear the wdt contents. the maximum time out period is when the 2 18 division ratio is selected. as an example, with a 32khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 2 18 division ratio and a minimum timeout of 7.8ms for the 2 8 division ration. clr wdt inst?u?tion 8-stage divide? wdt p?es?ale? we?~we0 ?its wdtc registe? reset mcu f sub f sub /? 8 8-to-1 mux clr ws?~ws0 (f sub /? 8 ~ f sub /? 18 ) wdt time-out (? 8 /f sub ~ ? 18 /f sub ) halt inst?u?tion watchdog timer
rev. 1.00 58 ??to?e? 01? ?01? rev. 1.00 59 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short delay , will be in a well defined state and ready to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the pow er-on res et, another res et exis ts in the form of a low v oltage res et, l vr, where a ful l re set is im plemented in sit uations whe re the power supply vol tage fa lls below a certain t hreshold. anot her t ype of re set i s whe n t he w atchdog t imer ove rflows a nd re sets t he microcontroller. all types of reset operations result in different register conditions being setup. reset functions there are five w ays in w hich a microcontroller res et can occur , through events occurring both internally and externally. power-on reset the m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s frst a pplied t o the microcontroller . as well as ensuring that the program memory begins execution from the frst memory address, a pow er-on reset also ensures that certain other registers are preset to know n conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. v dd powe?-on reset sst time-out t rstd note: t rstd is power-on delay with typical time = 50 ms power-on reset timing chart low voltage reset C lvr the mi crocontroller cont ains a low volt age reset circui t in orde r to moni tor the supply volt age of the de vice. t he l vr func tion i s a lways e nabled wi th a spe cifc l vr vol tage, v lvr . if t he suppl y voltage of t he de vice drops t o wi thin a range of 0.9v~v lvr suc h as m ight oc cur whe n c hanging the battery , the l vr will automatically reset the device internally and the l vrf bit in the ctrl register wi ll a lso b e se t t o 1 . fo r a v alid l vr si gnal, a l ow su pply v oltage, i .e., a v oltage i n t he range between 0.9v~ v lvr must exist for a time greater than that specifed by t lvr in the l vd/lvr characteristics. if the low supply voltage state does not exceed this value, the l vr will ignore the low supply voltag e and will not perform a reset function. the actual v lvr value can be selected by the l vs bits in the l vrc register . if the l vs7~lvs0 bits have any other value, which may perhaps occur due to adverse environmental conditions such as noise, the l vr will reset the device after 2~3 f lirc cloc k cycles. when this happens, the lrf bit in the ctrl register will be set to 1. after power on the register will have the value of 01010101b. note that the l vr function will be automatically disabled when the device enters the power down mode.
rev. 1.00 60 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 61 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom lvr inte?nal reset t rstd + t sst note: t rstd is power-on delay with typical time = 50 ms low voltage reset timing chart ? lvrc register bit 7 6 5 4 3 2 1 0 name lvs7 lvs6 lvs5 lvs ? lvs3 lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 1 0 1 0 1 0 1 bit 7~0 lvs7~lvs0 : lvr voltage select 01010101: 2.1v 00110011: 2.55v 10011001: 3.15v 10101010: 3.8v other values: generates a mcu reset C register is reset to por value when an actual low voltage condit ion occurs, as specifed by one of the four defned lvr voltage value above, an mcu reset will generated. the reset operation will be activated after 2~3 f lirc clock cycles. in this situation the register conte nts will remain the same after such a reset occurs. any register value, other than the four defned register values above, will also result in the generation of an mcu reset. the reset operation will be activated after 2~3 f lirc clock cycles. however , in this situation the register contents will be reset to the por value. ? ctrl register bit 7 6 5 4 3 2 1 0 name fsys ? n lvrf lrf wrf r/w r/w r/w r/w r/w p ? r 0 x 0 0 x: unknown bit 7 fsyson : f control in idle mode described elsewhere. bit 6~3 unimplemented, read as 0 bit 2 lvrf : lvr function reset fag 0: not occurred 1: occurred this bit is set to 1 when a specifc low voltage reset condition occurs. note that this bit can only be cleared to 0 by the application program. bit 1 lrf : lvr control register software reset fag 0: not occurred 1: occurred this bit is set to 1 by the l vrc control register contains any undefned l vr voltage register values. this in ef fect acts like a software-reset function. note that this bit can only be cleared to 0 by the application program. bit 0 wrf : wdt control register software reset fag described elsewhere.
rev. 1.00 60 ??to?e? 01? ?01? rev. 1.00 61 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom watchdog time-out reset during normal operation the w atchdog time-out reset during normal operation is the same as the hardw are low v oltage reset except that the w atchdog time-out fag t o will be set to 1. wdt time-out inte?nal reset t rstd + t sst note: t rstd is power-on delay with typical time = 16.7 ms wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of re set. mo st of t he c onditions re main unc hanged e xcept t hat t he pro gram count er a nd t he st ack pointer will be cle ared to 0 and the t o fag will be set to 1. refer to the a.c. characteristics for t sst details. wdt time-out inte?nal reset t sst wdt time-out reset during sleep or idle mode timing chart reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus register and are controlled by various microcontroller operations, su ch a s t he sl eep o r i dle mo de f unction o r w atchdog t imer. t he r eset f lags a re shown in the table: to pdf reset function 0 0 powe ? -on ? eset u u lvr ? eset du ? ing n ? rmal o ? sl ? w mode ope ? ation 1 u wdt time-out ? eset du ? ing n ? rmal o ? sl ? w mode ope ? ation 1 1 wdt time-out ? eset du ? ing idle o ? sleep mode ope ? ation u stands fo ? un ? hanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item reset function p ? og ? am counte ? reset to ze ? o inte ?? upts all inte ?? upts will ? e disa ? led wdt ? time base clea ? afte ? ? eset ? wdt ? egins ? ounting time ? modules time ? modules will ? e tu ? ned off input/ ? utput po ? ts i/ ? po ? ts will ? e setup as inputs sta ? k pointe ? sta ? k pointe ? will point to the top of the sta ? k the dif ferent kinds of resets all af fect the internal registers of the micr ocontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how eac h type of reset af fects the microcontroller internal registers. note that where more than one package type exists the table will refect the situation for the larger package type.
rev. 1.00 6 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 63 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom register HT66F0175 ht66f0185 reset (power on) lvr reset (normal operation) wdt time-out (normal operation) wdt time-out (idle or sleep)* mp0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu mp1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu bp ---- ---0 ---- ---0 ---- ---0 ---- ---u acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbhp ---- -xxx ---- -uuu ---- -uuu ---- -uuu tbhp ---- xxxx ---- uuuu ---- uuuu ---- uuuu status --00 xxxx --uu uuuu --1u uuuu --11 uuuu sm ? d 0000 0011 0000 0011 0000 0011 uuuu uuuu lvdc --00 -000 --00 -000 --00 -000 --uu -uuu integ ---- 0000 ---- 0000 ---- 0000 ---- uuuu intc0 -0-0 0-00 -0-0 0-00 -0-0 0-00 -u-u u-uu intc0 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc ? -000 -000 -000 -000 -000 -000 -uuu -uuu intc ? 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi0 --00 --00 --00 --00 --00 --00 --uu --uu mfi1 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi ? --00 --00 --00 --00 --00 --00 --uu --uu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu tmpc 0--- --00 0--- --00 0--- --00 u--- --uu tmpc 0--- -000 0--- -000 0--- -000 u--- -uuu wdtc 0101 0011 0101 0011 0101 0011 uuuu uuuu tbc 0011 0111 0011 0111 0011 0111 uuuu uuuu ctrl 0--- -x00 0--- -000 0--- -000 u--- -uuu lvrc 0101 0101 0101 0101 0101 0101 uuuu uuuu eea --00 0000 --00 0000 --00 0000 --uu uuuu eea -000 0000 -000 0000 -000 0000 -uuu uuuu eed 0000 0000 0000 0000 0000 0000 uuuu uuuu sad ? l (adrfs=0) xxxx ---- xxxx ---- xxxx ---- uuuu ---- sad ? l (adrfs=1) xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu sad ? h (adrfs=0) xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu sad ? h (adrfs=1) ---- xxxx ---- uuuu ---- uuuu ---- uuuu sadc0 0000 -000 0000 -000 0000 -000 uuuu -uuu sadc1 000- -000 000- -000 000- -000 uuu- -uuu sadc ? 0000 0000 0000 0000 0000 0000 uuuu uuuu pb -111 1111 -111 1111 -111 1111 -uuu uuuu pbc -111 1111 -111 1111 -111 1111 -uuu uuuu
rev. 1.00 6? ??to?e? 01? ?01? rev. 1.00 63 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom register HT66F0175 ht66f0185 reset (power on) lvr reset (normal operation) wdt time-out (normal operation) wdt time-out (idle or sleep)* pbpu -000 0000 -000 0000 -000 0000 -uuu uuuu tm ? c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- tm ? c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? dh 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? ah 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? rp 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh ----- --00 ---- --00 ---- --00 ---- --uu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0ah ----- --00 ---- --00 ---- --00 ---- --uu tm0rpl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0rph ----- --00 ---- --00 ---- --00 ---- --uu tm0c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0ah 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0rp 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- tm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dh ----- --00 ---- --00 ---- --00 ---- --uu tm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1ah ----- --00 ---- --00 ---- --00 ---- --uu tm1rpl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1rph ----- --00 ---- --00 ---- --00 ---- --uu cpc 1000 0001 1000 0001 1000 0001 uuuu uuuu pc -111 1111 -111 1111 -111 1111 -uuu uuuu pcc -111 1111 -111 1111 -111 1111 -uuu uuuu pcpu -000 0000 -000 0000 -000 0000 -uuu uuuu acerl 1111 1111 1111 1111 1111 1111 uuuu uuuu simc0 111- 0000 111- 0000 111- 0000 uuu- uuuu simc1 1000 0001 1000 0001 1000 0001 uuuu uuuu simd xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sima/simc ? 0000 0000 0000 0000 0000 0000 uuuu uuuu simt ? c 0000 0000 0000 0000 0000 0000 uuuu uuuu slcdc0 0000 0000 0000 0000 0000 0000 uuuu uuuu slcdc1 0000 0000 0000 0000 0000 0000 uuuu uuuu slcdc ? 0000 0000 0000 0000 0000 0000 uuuu uuuu
rev. 1.00 6 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 65 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom register HT66F0175 ht66f0185 reset (power on) lvr reset (normal operation) wdt time-out (normal operation) wdt time-out (idle or sleep)* slcdc3 0000 0000 0000 0000 0000 0000 uuuu uuuu slcdc ? ---- --00 ---- --00 ---- --00 ---- --uu sledc0 0101 0101 0101 0101 0101 0101 uuuu uuuu sledc1 --01 0101 --01 0101 --01 0101 --uu uuuu sledc1 ---- 0101 ---- 0101 ---- 0101 ---- uuuu ifs --00 0000 --00 0000 --00 0000 --uu uuuu ifs -000 0000 -000 0000 -000 0000 -uuu uuuu pd ---- 1111 ---- 1111 ---- 1111 ---- uuuu pdc ---- 1111 ---- 1111 ---- 1111 ---- uuuu pdpu ---- 0000 ---- 0000 ---- 0000 ---- uuuu usr 0000 1011 0000 1011 0000 1011 uuuu uuuu ucr1 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu ucr ? 0000 0000 0000 0000 0000 0000 uuuu uuuu brg xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu txr_rxr xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu eec ---- 0000 ---- 0000 ---- 0000 ---- uuuu note: u stands for unchanged x stands for unknown - stands for unimplemented
rev. 1.00 6? ??to?e? 01? ?01? rev. 1.00 65 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom input/output ports holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. these d evices p rovide b idirectional i nput/output l ines l abeled wi th p ort n ames p a~pd. t hese i /o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. a ll of thes e i/o ports can be used for input and output operations. for input operation, these ports are non-latch ing, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. register name bit 7 6 5 4 3 2 1 0 pawu pawu7 pawu6 pawu5 pawu ? pawu3 pawu ? pawu1 pawu0 pa pa7 pa6 pa5 pa ? pa3 pa ? pa1 pa0 pac pac7 pac6 pac5 pac ? pac3 pac ? pac1 pac0 papu papu7 papu6 papu5 papu ? papu3 papu ? papu1 papu0 pb pb6 pb5 pb ? pb3 pb ? pb1 pb0 pbc pbc6 pbc5 pbc ? pbc3 pbc ? pbc1 pbc0 pbpu pbpu6 pbpu5 pbpu ? pbpu3 pbpu ? pbpu1 pbpu0 pc pc6 pc5 pc ? pc3 pc ? pc1 pc0 pcc pcc6 pcc5 pcc ? pcc3 pcc ? pcc1 pcc0 pcpu pcpu6 pcpu5 pcpu ? pcpu3 pcpu ? pcpu1 pcpu0 i/o registers list C HT66F0175
rev. 1.00 66 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 67 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom register name bit 7 6 5 4 3 2 1 0 pawu pawu7 pawu6 pawu5 pawu ? pawu3 pawu ? pawu1 pawu0 pa pa7 pa6 pa5 pa ? pa3 pa ? pa1 pa0 pac pac7 pac6 pac5 pac ? pac3 pac ? pac1 pac0 papu papu7 papu6 papu5 papu ? papu3 papu ? papu1 papu0 pb pb6 pb5 pb ? pb3 pb ? pb1 pb0 pbc pbc6 pbc5 pbc ? pbc3 pbc ? pbc1 pbc0 pbpu pbpu6 pbpu5 pbpu ? pbpu3 pbpu ? pbpu1 pbpu0 pc pc6 pc5 pc ? pc3 pc ? pc1 pc0 pcc pcc6 pcc5 pcc ? pcc3 pcc ? pcc1 pcc0 pcpu pcpu6 pcpu5 pcpu ? pcpu3 pcpu ? pcpu1 pcpu0 pd pd3 pd ? pd1 pd0 pdc pdc3 pdc ? pdc1 pdc0 pdpu pdpu3 pdpu ? pdpu1 pdpu0 i/o registers list C ht66f0185 : unimplemented, read as 0. pawun : port a pin wake-up function control 0: disable 1: enable papun/pbpun/pcpun/pdpun : i/o pin pull-high function control 0: disable 1: enable pan/pbn/pcn/pdn : i/o port data bit 0: data 0 1: data 1 pacn/pbcn/pccn/pdcn : i/o pin type selection 0: output 1: input pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor . these pull-high resistors are selected using the relevant pull-high control registers and are implemented using weak pmos transistors. port a wake-up the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register.
rev. 1.00 66 ??to?e? 01? ?01? rev. 1.00 67 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom i/o port control registers each po rt h as i ts o wn c ontrol r egister, k nown a s p ac~pdc, wh ich c ontrols t he i nput/output configuration. w ith t his c ontrol re gister, e ach i/ o pi n wi th or wi thout pul l-high re sistors c an be reconfigured dynamically under software control. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. i/o port source current control these devices s upport dif ferent s ource current driving capability for each i/o port. w ith the corresponding selection register , sledc0 and sledc1, each i/o port can support four levels of the source current driving capability . users should refer to the d.c. charac teristics section to select the desired source current for different applications. register name bit 7 6 5 4 3 2 1 0 sledc0 pbps3 pbps ? pbps1 pbps0 paps3 paps ? paps1 paps0 sledc1 (HT66F0175) pcps3 pcps ? pcps1 pcps0 sledc1 (ht66f0185) pdps1 pdps0 pcps3 pcps ? pcps1 pcps0 i/o port source current control registers list sledc0 register bit 7 6 5 4 3 2 1 0 name pbps3 pbps ? pbps1 pbps0 paps3 paps ? paps1 paps0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 1 0 1 0 1 0 1 bit 7~6 pbps3~pbp2 : pb6~pb4 source current selection 00: source current = level 0 (min.) 01: source current = level 1 10: source current = level 2 11: source current = level 3 (max.) bit 5~4 pbps1~pbp0 : pb3~pb0 source current selection 00: source current = level 0 (min.) 01: source current = level 1 10: source current = level 2 11: source current = level 3 (max.) bit 3~2 paps3~pap2 : pa7~pa4 source current selection 00: source current = level 0 (min.) 01: source current = level 1 10: source current = level 2 11: source current = level 3 (max.) bit 1~0 paps1~pap0 : pa3~pa0 source current selection 00: source current = level 0 (min.) 01: source current = level 1 10: source current = level 2 11: source current = level 3 (max.)
rev. 1.00 68 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 69 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom sledc1 register C HT66F0175 bit 7 6 5 4 3 2 1 0 name pcps3 pcps ? pcps1 pcps0 r/w r/w r/w r/w r/w p ? r 0 1 0 1 bit 7~4 unimplemented, read as 0 bit 3~2 pcps3~pcp2 : pc6~pc4 source current selection 00: source current = level 0 (min.) 01: source current = level 1 10: source current = level 2 11: source current = level 3 (max.) bit 1~0 pcps1~pcp0 : pc3~pc0 source current selection 00: source current = level 0 (min.) 01: source current = level 1 10: source current = level 2 11: source current = level 3 (max.) sledc1 register C ht66f0185 bit 7 6 5 4 3 2 1 0 name pdps1 pdps0 pcps3 pcps ? pcps1 pcps0 r/w r/w r/w r/w r/w r/w r/w p ? r 0 1 0 1 0 1 bit 7~6 unimplemented, read as 0 bit 5~4 pdps1~pdp0 : pd3~pd0 source current selection 00: source current = level 0 (min.) 01: source current = level 1 10: source current = level 2 11: source current = level 3 (max.) bit 3~2 pcps3~pcp2 : pc6~pc4 source current selection 00: source current = level 0 (min.) 01: source current = level 1 10: source current = level 2 11: source current = level 3 (max.) bit 1~0 pcps1~pcp0 : pc3~pc0 source current selection 00: source current = level 0 (min.) 01: source current = level 1 10: source current = level 2 11: source current = level 3 (max.)
rev. 1.00 68 ??to?e? 01? ?01? rev. 1.00 69 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom pin-remapping functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by suppl ying pi ns wi th m ulti-functions, m any of t hese di fficulties c an be ove rcome. t he wa y i n which the pin function of each pin is selected is dif ferent for each function and a priority order is established whe re m ore t han one pi n func tion i s se lected si multaneously. addi tionally t here i s a register, ifs, to establish certain pin functions. the limited number of supplied pins in a package can i mpose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several dif ferent functions and providing a means of function selection, a wide range of dif ferent functions can be incorporated into even relatively small package sizes. if the pin-shared pin function have multiple outputs simultaneously, its pin names at the right side of the / sign can be used for higher priority. register name bit 7 6 5 4 3 2 1 0 ifs (HT66F0175) sd ? ps sdi_sdaps sck_sclps scsbps int1ps int0ps ifs (ht66f0185) sd ? ps1 sd ? ps0 sdi_sdaps sck_sclps scsbps txps rxps pin-remapping function selection registers list ifs register C HT66F0175 bit 7 6 5 4 3 2 1 0 name sd ? ps sdi_sdaps sck_sclps scsbps int1ps int0ps r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 sdops : sdo pin-remapping selection 0: sdo on pc2 1: sdo on pa1 bit 4 sdi_sdaps : sdi/sda pin-remapping selection 0: sdi/sda on pc3 1: sdi/sda on pa3 bit 3 sck_sclps : sck/scl pin-remapping selection 0: sck/cl on pc4 1: sck/cl on pb6 bit 2 scsbps : scs pin-remapping selection 0: scs on pa1 1: scs on pb5 bit 1 int1ps : int1 pin-remapping selection 0: int1 on pb1 1: int1 on pc5 bit 0 int0ps : int0 pin-remapping selection 0: int0 on pb0 1: int0 on pc6
rev. 1.00 70 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 71 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom ifs register C ht66f0185 bit 7 6 5 4 3 2 1 0 name sd ? ps1 sd ? ps0 sdi_sdaps sck_sclps scsbps txps rxps r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6~5 sdops1~sdops0 : sdo pin-remapping selection 00: sdo on pc3 01: sdo on pa1 10: undefned 11: sdo on pc2 bit 4 sdi_sdaps : sdi/sda pin-remapping selection 0: sdi/sda on pc4 1: sdi/sda on pa3 bit 3 sck_sclps : sck/scl pin-remapping selection 0: sck/cl on pc5 1: sck/cl on pb6 bit 2 scsbps : scs pin-remapping selection 0: scs on pc6 1: scs on pb5 bit 1 txps : tx pin-remapping selection 0: tx on pd2 1: tx on pb3 bit 0 rxps : rx pin-remapping selection 0: rx on pd1 1: rx on pb4 i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown.

??? ?? ? ? ? generic input/output structure
rev. 1.00 70 ??to?e? 01? ?01? rev. 1.00 71 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom

? ? ? ? ?
? ? - ? ? ? ? ? ? ? ? - a/d input/output structure programming considerations within the user program, one of the things frs t to consider is port initialisation. after a res et, all of the i/o data and port control registers will be set to high. this means that all i/o pins will be defaulted to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. if the port control registers are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. the power -on reset condition of the a/d converter control registers ensures that any a/d input pins, which are always shared with other i/o functions, will be setup as analog inputs after a reset. although these pins will be confgured as a/d inputs after a reset, the a/d converter will not be switched on. it i s t herefore i mportant t o not e t hat i f i t i s re quired t o use t hese pi ns a s i/ o di gital input pins or as other functions, the a/d converter control registers must be correctly programmed to remove the a/d funct ion. note al so that as the a/d channel is enabled, any int ernal pull-high resistor connections will be removed. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function.
rev. 1.00 7 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 73 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom timer modules C tm one of the most fundamental functions in any microcontroller devices is the ability to control and measure time. t o implement time related functions the device includes several t imer modules, generally abbrevia ted to the name tm. the tms are multi-purpose timi ng units and serve to provide operations such as t imer/counter, input capture, compare match output and single pulse output as we ll a s be ing t he fun ctional uni t for t he ge neration of pw m si gnals. e ach of t he t ms ha s t wo interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the dif ferent tm types are described here with more detailed information provided in the individual compact, standard and periodic tm sections. introduction the devices contain two or three tms depending upon which device is selected with each tm having a reference name of tm0, tm1, and tm2. each individual tm can be categorised as a certain type, namely compact t ype tm, standard t ype tm or periodic t ype tm. although similar in nature, the dif ferent tm types vary in their feature complexity . the common features to all of the compact, standard and periodic tms will be described in this section and the detailed operation regarding each of the tm types will be described in separate sections. the main features and differences between the three types of tms are summarised in the accompanying table. tm function ctm stm ptm time ? /counte ? input captu ? e compa ? e mat ? h ? utput pwm channels 1 1 1 single pulse ? utput 1 1 pwm alignment edge edge edge pwm adjustment pe ? iod & duty duty o ? pe ? iod duty o ? pe ? iod duty o ? pe ? iod tm function summary each device in the series contains a specifc number of either compact t ype, standard t ype and periodic t ype tm units which are shown in the table together with their individual reference name, tm0~tm2. device tm0 tm1 tm2 HT66F0175 10- ? it ptm 10- ? it ptm ht66f0185 16- ? it stm 10- ? it ptm 16- ? it ctm tm name/type reference tm operation the dif ferent types of tm of fer a diverse range of functions, from simple timing operations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a free running count-up counter whose value is then compared with the value of pre-programmed internal comparators. w hen t he f ree r unning c ount-up c ounter h as t he sa me v alue a s t he p re-programmed comparator, known a s a c ompare m atch si tuation, a t m i nterrupt si gnal wi ll be ge nerated whi ch can clear the counter and perhaps also change the condition of the tm output pin. the internal tm counter is driven by a user selectable clock source, which can be an internal clock or an external pin.
rev. 1.00 7? ??to?e? 01? ?01? rev. 1.00 73 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom tm clock source the c lock so urce wh ich d rives t he m ain c ounter i n e ach t m c an o riginate f rom v arious so urces. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of the system clock, f sys , or the internal high clock, f h , the f tbc clock source or the external tckn pin. the tckn pin cloc k source is used to allow an external signal to drive the tm as an external clock source for event counting. tm interrupts the compact, standard or periodic type tm has two internal interrupt, one for each of the internal comparator a or comparator p , which generate a tm interrupt when a compare match condition occurs. when a tm interrupt is generated, it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register . this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm i f se lected u sing t he t nck2~tnck0 b its. t he t m i nput p in c an b e c hosen t o h ave e ither a rising or falling active edge. the tckn pin is also used as the external trigger input pin in single pulse output mode for the stm and ptm respectively. the tms each have one output pin with the label tpn. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn output pin is also the pin where the tm generates the pwm output waveform. the tpn pin acts as an input when the tm is setup to operate in the capture input mode. as the tpn pins are pin-shared with other functions, the tpn pin function is enabled or disabled according to the internal tm on/of f control, operation mode and output control settings. when the corresponding tm confguration selects the tpn pin to be used as an output pin, the associated pin will be setup as an external tm output pin. if the tm confguration selects the tpn pin to be setup as an input pin, the input signal supplied on the associated pin can be de rived from a n e xternal si gnal a nd ot her pi n-shared out put funct ion. if t he tm c onfguration determines that the tpn pin function is not used, the associated pin will be controlled by other pin-shared functions. the details of the tpn pin for each tm type and device are provided in the accompanying table. device stm ptm ctm register HT66F0175 tck0; tp0 tck1; tp1 tmpc ht66f0185 tck0; tp0 tck1; tp1 tck ? ; tp ? tmpc tm external pins
rev. 1.00 7 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 75 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom tm input/output pin control register selecting t o ha ve a t m i nput/output or whe ther t o re tain i ts ot her sha red func tion i s i mplemented using t he r elevant p in-shared f unction se lection r egisters, wi th t he c orresponding se lection b its i n each pin-shared function register corresponding to a tm input/output pin. confguring the selection bits correctly will setup the corresponding pin as a tm input/output. the details of the pin-shared function selection are described in the pin-shared function section. register name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmpc (HT66F0175) cl ? p t1cp t0cp tmpc (ht66f0185) cl ? p t ? cp t1cp t0cp tm pin control register list tm0 (ptm) pa0/tp0 t0cp pa0 ?utput fun?tion 0 1 ?utput captu?e input t0capts pb?/tck0 tck input 0 1 pa0 0 1 1 0 tm0 function pin control block diagram C HT66F0175 only tm0 (stm) pa0/tp0 t0cp pa0 ?utput fun?tion 0 1 ?utput captu?e input pb?/tck0 tck input 0 1 pa0 1 0 tm0 function pin control block diagram C ht66f0185 only tm1 (ptm) pa7/tp1 t1cp pa7 ?utput fun?tion 0 1 ?utput captu?e input t1capts pa?/tck1 tck input 0 1 pa7 0 1 1 0 tm1 function pin control block diagram C HT66F0175/ht66f0185
rev. 1.00 7? ??to?e? 01? ?01? rev. 1.00 75 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom tm2 (ctm) pb3/tp? t?cp pb3 ?utput fun?tion 0 1 ?utput pa6/tck? tck input 0 1 pb3 tm2 function pin control block diagram C ht66f0185 only note: 1. the i/o register data bits shown are used for tm output inversion control. 2. in the capture input mode, the tm pin control register must never enable more than one tm input. tmpc register C HT66F0175 bit 7 6 5 4 3 2 1 0 name cl ? p t1cp t0cp r/w r/w r/w r/w p ? r 0 0 0 bit 7 clop : clo pin control 0: disable 1: enable bit 6~2 unimplemented, read as 0 bit 1 t1cp : tp1 pin control 0: disable 1: enable bit 0 t0cp : tp0 pin control 0: disable 1: enable tmpc register C ht66f0185 bit 7 6 5 4 3 2 1 0 name cl ? p t ? cp t1cp t0cp r/w r/w r/w r/w r/w p ? r 0 0 0 0 bit 7 clop : clo pin control 0: disable 1: enable bit 6~3 unimplemented, read as 0 bit 2 t2cp : tp2 pin control 0: disable 1: enable bit 1 t1cp : tp1 pin control 0: disable 1: enable bit 0 t0cp : tp0 pin control 0: disable 1: enable
rev. 1.00 76 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 77 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom programming considerations the tm counter registers and the capture/compare ccra and ccrp registers, being either 10- bit or 16-bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these register pairs must be carried out in a specifc way . the important point to note is that data transfer to and from the 8-bit buf fer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. as the ccra and ccrp registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specifc way as described above, it is recommended to use the mov instruction to access the ccra and ccrp low byte registers, named tmnal and tmnrpl, using the following access procedures. accessing the ccra or ccrp low byte registers without following these access procedures will result in unpredictable values. data bus 8-?it buffe? tmndh tmndl tmnah tmnal tmn counte? registe? (read only) tmn ccra registe? (read/w?ite) tmnrph tmnrpl ptm ccrp registe? (read/w?ite) the following steps show the read and write procedures: ? writing data to ccra or ccrp ? step 1. w rite data to low byte tmnal or tmnrpl C note that here data is only written to the 8-bit buffer. ? step 2. w rite data to high byte tmnah or tmnrph C here data is written directly to the high byte regis ters and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccra or ccrp ? step 1. read data from the high byte tmndh, tmnah or tmnrph C here d ata i s r ead d irectly f rom t he hi gh b yte r egisters a nd si multaneously d ata i s l atched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tmndl, tmnal or tmnrpl C this step reads data from the 8-bit buffer.
rev. 1.00 76 ??to?e? 01? ?01? rev. 1.00 77 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom compact type tm C ctm the com pact t ype t m, ct m, i s onl y c ontained i n t he ht 66f0185 de vice. al though t he si mplest form of the tm types, the compact tm type still contains three operating modes, which are compare match output, t imer/event counter and pwm output modes. the compact tm can also be controlled with an external input pin and can drive one external output pin. device tm core tm no. tm input pin tm output pin ht66f0185 16- ? it ctm tm ? tck ? tp ? f sys f sys /? f h /6? f h /16 f tbc tckn 000 001 010 011 100 101 110 111 tnck?~tnck0 16-?it count-up counte? 8-?it compa?ato? p ccrp ?8~?15 ?0~?15 16-?it compa?ato? a tn?n tnpau compa?ato? a mat?h compa?ato? p mat?h counte? clea? 0 1 ?utput cont?ol pola?ity cont?ol pin cont?ol tpn tn?c tnm1? tnm0 tni?1? tni?0 tnaf inte??upt tnpf inte??upt tnp?l tncp ccra tncclr f h /8 compact type tm block diagram C n = 2 for ht66f0185 only compact tm operation the compact tm core is a 16-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p . these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp is eight-bit w ide w hose value is compared w ith the highes t three bits in the counter while the ccra is sixteen-bit wide and therefore compares with all counter bits. the onl y way of changing the value of the 16-bit counte r using the appl ication program , is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
rev. 1.00 78 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 79 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom compact type tm register description overall operation of the compact tm is controlled using a series of registers. a read only register pair e xists t o st ore t he i nternal c ounter 16 -bit va lue, whi le a re ad/write re gister pa ir e xists t o st ore the internal 16-bit ccra value. there is also a read/write register used to store the internal 8-bit ccrp value. the remaining two registers are control registers which setup the dif ferent operating and control modes. register name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmnc0 tnpau tnck ? tnck1 tnck0 tn ? n tmnc1 tnm1 tnm0 tni ? 1 tni ? 0 tn ? c tnp ? l tndpx tncclr tmndl d7 d6 d5 d ? d3 d ? d1 d0 tmndh d15 d1 ? d13 d1 ? d11 d10 d9 d8 tmnal d7 d6 d5 d ? d3 d ? d1 d0 tmnah d15 d1 ? d13 d1 ? d11 d10 d9 d8 tmnrp tnrp7 tnrp6 tnrp5 tnrp ? tnrp3 tnrp ? tnrp1 tnrp0 16-bit compact tm registers list C n = 2 for for ht66f0185 only tmndl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d ? d3 d ? d1 d0 r/w r r r r r r r r p ? r 0 0 0 0 0 0 0 0 bit 7~0 tmn counter low byte register bit 7 ~ bit 0 tmn 16-bit counter bit 7 ~ bit 0 tmndh register bit 7 6 5 4 3 2 1 0 name d15 d1 ? d13 d1 ? d11 d10 d9 d8 r/w r r r r r r r r p ? r 0 0 0 0 0 0 0 0 bit 7~0 tmn counter high byte register bit 7 ~ bit 0 tmn 16-bit counter bit 15 ~ bit 8 tmnal register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 0 bit 7~0 tmn ccra low byte register bit 7 ~ bit 0 tmn 16-bit ccra bit 7 ~ bit 0 tmnah register bit 7 6 5 4 3 2 1 0 name d15 d1 ? d13 d1 ? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 0 bit 1~0 tmn ccra high byte register bit 7 ~ bit 0 tmn 16-bit ccra bit 15 ~ bit 8
rev. 1.00 78 ??to?e? 01? ?01? rev. 1.00 79 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom tmnc0 register bit 7 6 5 4 3 2 1 0 name tnpau tnck ? tnck1 tnck0 tn ? n r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 bit 7 tnpau : tmn counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tmn will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0 : select tmn counter clock 000: f /4 001: f 010: f h /16 011: f h /64 100: f tbc 101: f h /8 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tmn. t he external pin clock source can be chosen to be active on the rising or falling edge. the cloc k source f is the system clock, while f h and f tbc are other internal clocks, the detai ls of which can be found in the oscillator section. bit 3 tnon : tmn counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tmn. setting the bit high enables the counter to run while clearing the bit disables the tmn. clearing this bit to zero will stop the counter from counting and turn of f the tmn which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. if the tmn is in the compare match output mode then the tmn output pin will be reset to its initial condition, as specifed by the tnoc bit, when the tnon bit changes from low to high. bit 2~0 unimplemented, read as 0
rev. 1.00 80 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 81 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom tmnc1 register bit 7 6 5 4 3 2 1 0 name tnm1 tnm0 tni ? 1 tni ? 0 tn ? c tnp ? l tndpx tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 0 bit 7~6 tnm1~tnm0 : select tmn operating mode 00: compare match output mode 01: undefned 10: pwm mode 11: t imer/counter mode these b its se tup t he r equired o perating m ode f or t he t mn. t o e nsure r eliable o peration the tmn should be switched of f before any changes are made to the tnm1 and tnm0 bits. in the t imer/counter mode, the tmn output pin control will be disabled. bit 5~4 tnio1~tnio0 : select tpn pin output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused these two bits are used to determine how the tmn output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tmn is running. in t he com pare ma tch out put mode , t he t nio1 a nd t nio0 bi ts de termine how t he tmn output pin changes state when a compare match occurs from the comparator a. the t mn ou tput pi n c an be se tup t o swi tch hi gh, swi tch l ow or t o t oggle i ts pr esent state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tmn output pin should be setup using the tnoc bit in the tmnc1 register . note that the output level requested by the tnio1 and tnio0 bits must be dif ferent from the initial value setup using the tnoc bit otherwise no change will occur on the tmn output pin when a compare match occurs. after the tmn output pin changes state, it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm mode, the tnio1 and tnio0 bits determine how the tmn output pin changes state when a certain compare match condition occurs. the pwm output function i s m odified b y c hanging t hese t wo b its. i t i s n ecessary t o o nly c hange t he values of t he t nio1 a nd t nio0 bi ts onl y a fter t he t mn ha s be en swi tched of f. unpredictable pwm outputs will occur if the t nio1 and t nio0 bits are changed when the tmn is running.
rev. 1.00 80 ??to?e? 01? ?01? rev. 1.00 81 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom bit 3 tnoc : tpn output control compare match output mode 0: initial low 1: initial high pwm output mode 0: active low 1: active high this is the output control bit for the tmn output pin. its operation depends upon whether tmn is being used in the compare match output mode or in the pwm mode. it has no ef fect if the tmn is in the t imer/counter mode. in the compare match output mode it determines the logic level of the tmn output pin before a compare match oc curs. in t he pwm mode i t det ermines i f t he pwm si gnal i s a ctive hi gh or active low. bit 2 tnpol : tpn output polarity control 0: non-inverted 1: inverted this bit controls the polarity of the tpn output pin. when the bit is set high the tmn output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the tmn is in the t imer/counter mode. bit 1 tndpx : tmn pwm duty/period control 0: ccrp C period; ccra C duty 1: ccrp C duty; ccra C period this b it d etermines wh ich o f t he c cra a nd c crp r egisters a re u sed f or p eriod a nd duty control of the pwm waveform. bit 0 tncclr : tmn counter clear condition selection 0: tmn comparator p match 1: tmn comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he compact tm contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm mode. tmnrp register bit 7 6 5 4 3 2 1 0 name tnrp7 tnrp6 tnrp5 tnrp ? tnrp3 tnrp ? tnrp1 tnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 0 bit 7~0 tnrp7~tnrp0 : tmn ccrp 8-bit register, compared with the tmn counter bit 15~bit 8 comprartor p match period 0: 65535 tmn clocks 1~255: 256 (1~255) tmn clocks these eight bits are used to setup the value on the internal ccrp 8-bit register , which are then compared with the internal counter s highest eight bits. the result of this comparison c an be se lected t o c lear t he i nternal c ounter i f t he t ncclr bi t i s se t t o zero. set ting t he t ncclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value.
rev. 1.00 8 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 83 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom compact type tm operation modes the compact t ype tm can operate in one of three operating modes, compare match output mode, pwm mo de o r t imer/counter mo de. t he o perating m ode i s se lected u sing t he t nm1 a nd t nm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the tncclr bit is low , there are two ways in which the counter can be cleared. one is when a c ompare m atch o ccurs f rom c omparator p , t he o ther i s wh en t he c crp b its a re a ll z ero wh ich allows the counter to overfow . here both tnaf and tnpf interrupt request fags for the comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tmnpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 1-bit, ffff hex, value, however here the tnaf interrupt request fag will not be generated. as t he n ame o f t he m ode su ggests, a fter a c omparison i s m ade, t he t mn o utput p in wi ll c hange state. the tmn output pin condition however only changes state when a tnaf interrupt request fag is generated after a compare match occurs from comparator a. the tnpf interrupt request fag, generated from a compare match occurs from comparator p , will have no ef fect on the tmn output pin. the way in which the tmn output pin changes state are determined by the condition of the tnio1 and tnio0 bits in the tmnc1 register . the tmn output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tmn output pin, which is setup after the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place.
rev. 1.00 8? ??to?e? 01? ?01? rev. 1.00 83 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom counte? value 0xffff ccrp ccra tn?n tnpau tnp?l ccrp int . flag tnpf ccra int . flag tnaf tmn ?/p pin time ccrp=0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed ?y ccrp value pause resume stop counte? resta?t tncclr = 0; tnm [1:0] = 00 ?utput pin set to initial level low if tn?c=0 ?utput toggle with tnaf flag note tni? [1:0] = 10 a?tive high ?utput sele?t he?e tni? [1:0] = 11 toggle ?utput sele?t ?utput not affe?ted ?y tnaf flag. remains high until ?eset ?y tn?n ?it ?utput pin reset to initial value ?utput ?ont?olled ?y othe? pin-sha?ed fun?tion ?utput inve?ts when tnp?l is high compare match output mode C tncclr = 0 note: 1. w ith tncclr = 0, a comparator p match will clear the counter 2. the tmn output pin controlled only by tnaf fag 3. the output pin is reset to its initial state by tnon bit rising edge 4. n = 2 for ht66f0185 only
rev. 1.00 8 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 85 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom counte? value 0xffff ccrp ccra tn?n tnpau tnp?l tmn ? / p pin time ccra=0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed ?y ccra value pause resume stop counte? resta?t tncclr = 1; tnm [1:0] = 00 ?utput pin set to initial level low if tn?c=0 ?utput toggle with tnaf flag note tni? [1:0] = 10 a?tive high ?utput sele?t he?e tni? [1:0] = 11 toggle ?utput sele?t ?utput not affe?ted ?y tnaf flag. remains high until ?eset ?y tn?n ?it ?utput pin reset to initial value ?utput ?ont?olled ?y othe? pin-sha?ed fun?tion ?utput inve?ts when tnp?l is high tnpf not gene?ated no tnaf flag gene?ated on ccra ove?flow ?utput does not ?hange ccra int . flag tnaf ccrp int . flag tnpf compare match output mode C tncclr = 1 note: 1. w ith tncclr = 1, a comparator a match will clear the counter 2. the tmn output pin is controlled only by tnaf fag 3. the tmn output pin is reset to initial state by tnon rising edge 4. the tnpf fags is not generated when tncclr = 1 5. n = 2 for ht66f0185 only timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tmn output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tmn output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively . the pwm function within the tmn is useful for applications which require functions such as motor control, hea ting cont rol, i llumination cont rol e tc. by providing a si gnal of fxe d frequenc y but of varying d uty c ycle o n t he t mn o utput p in, a sq uare wa ve ac wa veform c an b e g enerated wi th varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated
rev. 1.00 8? ??to?e? 01? ?01? rev. 1.00 85 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom waveform i s e xtremely fl exible. in t he pwm m ode, t he t ncclr bi t ha s no e ffect on t he pwm operation. bot h of t he ccra a nd ccrp re gisters a re use d t o ge nerate t he pw m wave form, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register . the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. ? 16-bit ctm, pwm mode, edge-aligned mode, tndpx=0 ccrp 1~255 0 pe ? iod ccrp ? 56 65536 duty ccra if f sys = 16mhz, tmn clock source is f sys /4, ccrp = 2 and ccra = 128, the tmn pwm output frequency = (f sys /4) / (2256) = f sys /2048 = 7.8125 khz, duty = 128/(2256)= 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ? 16-bit ctm, pwm mode, edge-aligned mode, tndpx=1 ccrp 1~255 0 pe ? iod ccra duty ccrp ? 56 65536 the pwm out put peri od is determi ned by the ccra regi ster value together wit h the tmn cl ock while the pwm duty cycle is defned by the (ccrp256) value except when the ccrp value is equal to 0.
rev. 1.00 86 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 87 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom counte? value ccrp ccra tn?n tnpau tnp?l tmn ? / p pin ( tn ?c =1) time counte? ?lea? ed ?y ccrp pause resume counte ? stop if tn?n ?it low counte? reset when tn?n ?etu?ns high tndpx = 0; tnm [1:0] = 10 pwm duty cy? le set ?y ccra pwm ? esumes ope?ation ? utput ?ont ?olled ? y othe? pin-sha?ed fun?tion ?utput inve?ts when tnp?l = 1 pwm pe ? iod set ?y ccrp tmn ? / p pin ( tn ?c =0) ccra int . flag tnaf ccrp int . flag tnpf pwm output mode C tndxp = 0 note: 1. here tndpx = 0 C counter cleared by ccrp 2. a counter clear sets pwm period 3. the internal pwm function continues even when tnio1, tnio0 = 00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n = 2 for ht66f0185 only
rev. 1.00 86 ??to?e? 01? ?01? rev. 1.00 87 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom counte? value ccrp ccra tn?n tnpau tnp?l ccrp int . flag tnpf ccra int . flag tnaf tmn ? / p pin ( tn ?c =1) time counte? ?lea?ed ?y ccra pause resume counte? stop if tn?n ?it low counte? reset when tn?n ?etu?ns high tndpx = 1; tnm [1:0] = 10 pwm duty cy?le set ?y ccrp pwm ?esumes ope?ation ?utput ?ont?olled ?y othe? pin-sha?ed fun?tion ?utput inve?ts when tnp?l = 1 pwm pe?iod set ?y ccra tmn ? / p pin ( tn ?c =0) pwm output mode C tndxp = 1 note: 1. here tndpx = 1 C counter cleared by ccra 2. a counter clear sets pwm period 3. the internal pwm function continues even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n = 2 for ht66f0185 only
rev. 1.00 88 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 89 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom standard type tm C stm the standard t ype tm, stm, is only contained in the ht66f0185 device. the standard t ype tm contains fve operating modes, which are compare match output, t imer/event counter , capture input, single pulse output and pwm output modes. the standard tm can also be controlled with an external input pin and can drive one external output pin. device tm core tm no. tm input pin tm output pin ht66f0185 16- ? it stm tm0 tck0 tp0 f sys f sys /? f h /6? f h /16 f tbc tckn 000 001 010 011 100 101 110 111 tnck?~tnck0 16-?it count-up counte? 8-?it compa?ato? p ccrp ?8~?15 ?0~?15 16-?it compa?ato? a tn?n tnpau compa?ato? a mat?h compa?ato? p mat?h counte? clea? 0 1 ?utput cont?ol pola?ity cont?ol pin cont?ol tpn tn?c tnm1? tnm0 tni?1? tni?0 tnaf inte??upt tnpf inte??upt tnp?l tncp ccra tncclr edge dete?to? tni?1? tni?0 f h /8 standard type tm block diagram C n = 0 for ht66f0185 only standard tm operation the size of standard tm is 16-bit wide and its core is a 16-bit count-up counter which is driven by a user selectable internal or externa l clock source. there are also two internal comparators with the names, comparato r a and comparator p . these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp comparator is 8-bit wide whose value is compared the with highest eight bits in the counte r while the ccra is the sixteen bits and therefore compares all counter bits. the onl y way of changing the value of the 16-bit counte r using the appl ication program , is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when thes e conditions occur , a tm interrupt s ignal w ill als o us ually be generated. the s tandard type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
rev. 1.00 88 ??to?e? 01? ?01? rev. 1.00 89 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom standard type tm register description overall operation of the standard tm is controlled using a series of registers. a read only register pair e xists t o st ore t he i nternal c ounter 16 -bit va lue, whi le a re ad/write re gister pa ir e xists t o st ore the i nternal 16-bi t ccra va lue. t he t mnrp regi ster i s use d t o store t he 8-bi t ccrp val ue. t he remaining two registers are control registers which setup the different operating and control modes. register name bit 7 6 5 4 3 2 1 0 tmnc0 tnpau tnck ? tnck1 tnck0 tn ? n tmnc1 tnm1 tnm0 tni ? 1 tni ? 0 tn ? c tnp ? l tndpx tncclr tmndl d7 d6 d5 d ? d3 d ? d1 d0 tmndh d15 d1 ? d13 d1 ? d11 d10 d9 d8 tmnal d7 d6 d5 d ? d3 d ? d1 d0 tmnah d15 d1 ? d13 d1 ? d11 d10 d9 d8 tmnrp tnrp7 tnrp6 tnrp5 tnrp ? tnrp3 tnrp ? tnrp1 tnrp0 16-bit standard tm registers list C n = 0 for ht66f0185 only tmndl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d ? d3 d ? d1 d0 r/w r r r r r r r r p ? r 0 0 0 0 0 0 0 0 bit 7~0 tmn counter low byte register bit 7 ~ bit 0 tmn 16-bit counter bit 7 ~ bit 0 tmndh register bit 7 6 5 4 3 2 1 0 name d15 d1 ? d13 d1 ? d11 d10 d9 d8 r/w r r r r r r r r p ? r 0 0 0 0 0 0 0 0 bit 7~0 tmn counter high byte register bit 7 ~ bit 0 tmn 16-bit counter bit 15 ~ bit 8 tmnal register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 0 bit 7~0 tmn ccra low byte register bit 7 ~ bit 0 tmn 16-bit ccra bit 7 ~ bit 0 tmnah register bit 7 6 5 4 3 2 1 0 name d15 d1 ? d13 d1 ? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 0 bit 7~0 tmn ccra high byte register bit 7 ~ bit 0 tmn 16-bit ccra bit 15 ~ bit 8
rev. 1.00 90 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 91 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom tmnc0 register bit 7 6 5 4 3 2 1 0 name tnpau tnck ? tnck1 tnck0 tn ? n r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 bit 7 tnpau : tmn counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tmn will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0 : select tmn counter clock 000: f /4 001: f 010: f h /16 011: f h /64 100: f tbc 101: f h /8 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tmn. t he external pin clock source can be chosen to be active on the rising or falling edge. the cloc k source f is the system clock, while f h and f tbc are other internal clocks, the detai ls of which can be found in the oscillator section. bit 3 tnon : tmn counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tmn. setting the bit high enables the counter to run while clearing the bit disables the tmn. clearing this bit to zero will stop the counter from counting and turn of f the tmn which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. if the tmn is in the compare match output mode then the tmn output pin will be reset to its initial condition, as specifed by the tnoc bit, when the tnon bit changes from low to high. bit 2~0 unimplemented, read as 0
rev. 1.00 90 ??to?e? 01? ?01? rev. 1.00 91 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom tmnc1 register bit 7 6 5 4 3 2 1 0 name tnm1 tnm0 tni ? 1 tni ? 0 tn ? c tnp ? l tndpx tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 0 bit 7~6 tnm1~tnm0 : select tmn operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these b its se tup t he r equired o perating m ode f or t he t mn. t o e nsure r eliable o peration the tmn should be switched of f before any changes are made to the tnm1 and tnm0 bits. in the t imer/counter mode, the tmn output pin control will be disabled. bit 5~4 tnio1~tnio0 : select tpn external pin function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm output mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tpn 01: input capture at falling edge of tpn 10: input capture at rising/falling edge of tpn 11: input capture disabled timer/counter mode unused these two bits are used to determine how the tmn output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tmn is running. in t he com pare ma tch out put mode , t he t nio1 a nd t nio0 bi ts de termine how t he tmn output pi n cha nges state when a com pare matc h occ urs from the comparat or a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tmn output pin should be setup using the tnoc bit in the tmnc1 register . note that the output level requested by the tnio1 and tnio0 bits must be dif ferent from the initial value setup using the tnoc bit otherwise no change will occur on the tmn output pin when a compare match occurs. after the tmn output pin changes state, it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm mode, the tnio1 and tnio0 bits determine how the tmn output pin changes state when a certain compare match condition occurs. the pwm output function i s m odified b y c hanging t hese t wo b its. i t i s n ecessary t o o nly c hange t he values of t he t nio1 a nd t nio0 bi ts onl y a fter t he t mn ha s be en swi tched of f. unpredictable pwm outputs will occur if the t nio1 and t nio0 bits are changed when the tmn is running.
rev. 1.00 9 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 93 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom bit 3 tnoc : tmn tpn output control compare match output mode 0: initial low 1: initial high pwm output mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tmn output pin. its operation depends upon whether t mn is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no ef fect if the tmn is in the t imer/counter mode. in the compare match output mode it determines the logic level of the tmn output pin before a compare match occurs. in the pwm mode/single pulse output mode it determines if the pwm signal is active high or active low. bit 2 tnpol : tmn tpn output polarity control 0: non-inverted 1: inverted this bit controls the polarity of the tpn output pin. when the bit is set high the tmn output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the tmn is in the t imer/counter mode. bit 1 tndpx : tmn pwm duty/period control 0: ccrp C period; ccra C duty 1: ccrp C duty; ccra C period this b it d etermines wh ich o f t he c cra a nd c crp r egisters a re u sed f or p eriod a nd duty control of the pwm waveform. bit 0 tncclr : tmn counter clear condition selection 0: comparator p match 1: comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he standard tm contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm output, single pulse output or capture input mode.
rev. 1.00 9? ??to?e? 01? ?01? rev. 1.00 93 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom tmnrp register bit 7 6 5 4 3 2 1 0 name tnrp7 tnrp6 tnrp5 tnrp ? tnrp3 tnrp ? tnrp1 tnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 0 bit 7~0 tnrp7~tnrp0 : tmn ccrp 8-bit register, compared with the tmn counter bit 15~bit 8 comparator p match period = 0: 65536 tmn clocks 1~255: (1~255) 256 tmn clocks these eight bits are used to setup the value on the internal ccrp 8-bit register , which are then compared with the internal counter s highest eight bits. the result of this comparison c an be se lected t o c lear t he i nternal c ounter i f t he t ncclr bi t i s se t t o zero. set ting t he t ncclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. clearing a ll e ight bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value. standard type tm operation modes the standard t ype tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the tncclr bit is low , there are two ways in which the counter can be cleared. one is when a c ompare m atch f rom c omparator p , t he o ther i s wh en t he c crp b its a re a ll z ero wh ich a llows the c ounter t o ove rfow. he re bot h t naf a nd t npf i nterrupt re quest fa gs for com parator a a nd comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr i s h igh n o t npf i nterrupt r equest fa g wi ll b e g enerated. i n t he c ompare ma tch ou tput mode, the ccra can not be set to 0. as t he na me of t he m ode sugge sts, a fter a c omparison i s m ade, t he t mn out put pi n, wi ll c hange state. the tmn output pin condition however only changes state when a tnaf interrupt request fag is generated after a compare match occurs from comparator a. the tnpf interrupt request fag, generated from a compare match occurs from comparator p , will have no ef fect on the tmn output pin. the way in which the tmn output pin changes state are determined by the condition of the tnio1 and tnio0 bits in the tmnc1 register . the tmn output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tmn output pin, which is setup after the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place.
rev. 1.00 9 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 95 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom counte? value 0xffff ccrp ccra tn?n tnpau tnp?l ccrp int . flag tnpf ccra int . flag tnaf tmn ? / p pin time ccrp=0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed ?y ccrp value pause resume stop counte? resta?t tncclr = 0; tnm [1:0] = 00 ?utput pin set to initial level low if tn?c=0 ?utput toggle with tnaf flag note tni? [1:0] = 10 a?tive high ?utput sele?t he?e tni? [1:0] = 11 toggle ?utput sele?t ?utput not affe?ted ?y tnaf flag. remains high until ?eset ?y tn?n ?it ?utput pin reset to initial value ?utput ?ont?olled ?y othe? pin-sha?ed fun?tion ?utput inve?ts when tnp?l is high compare match output mode C tncclr = 0 note: 1. w ith tncclr=0 a comparator p match will clear the counter 2. the stmn output pin is controlled only by the tnaf fag 3. the output pin is reset to itsinitial state by a tnon bit rising edge 4. n = 0 for ht66f0185 only
rev. 1.00 9? ??to?e? 01? ?01? rev. 1.00 95 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom counte? value 0xffff ccrp ccra tn?n tnpau tnp?l ccrp int . flag tnpf ccra int . flag tnaf tmn ? / p pin time ccra=0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed ?y ccra value pause resume stop counte? resta?t tncclr = 1; tnm [1:0] = 00 ?utput pin set to initial level low if tn?c=0 ?utput toggle with tnaf flag note tni? [1:0] = 10 a?tive high ?utput sele?t he?e tni? [1:0] = 11 toggle ?utput sele?t ?utput not affe?ted ?y tnaf flag. remains high until ?eset ?y tn?n ?it ?utput pin reset to initial value ?utput ?ont?olled ?y othe? pin-sha?ed fun?tion ?utput inve?ts when tnp?l is high tnpf not gene?ated no tnaf flag gene?ated on ccra ove?flow ?utput does not ?hange compare match output mode C tncclr = 1 note: 1. w ith tncclr=1 a comparator a match will clear the counter 2. the tmn output pin is controlled only by the mnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. a tnpf fag is not generated when tncclr=1 5. n = 0 for ht66f0185 only
rev. 1.00 96 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 97 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tmn output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tmn output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to se lect t his mode , bit s t nm1 and t nm0 i n t he t mnc1 regi ster should be se t t o 10 respe ctively and also the tnio1 and tnio0 bits should be set to 10 respectively . the pwm function within the t mn i s use ful for a pplications whi ch re quire func tions suc h a s m otor c ontrol, he ating c ontrol, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tmn output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pw m m ode, t he t ncclr bi t ha s no e ffect a s t he pw m period. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register . the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tmn output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. ? 16-bit stm, pwm mode, edge-aligned mode, tndpx=0 ccrp 1~255 0 pe ? iod ccrp ? 56 65536 duty ccra if f sys = 16mhz, tmn clock source is f sys /4, ccrp = 2 and ccra = 128, the tmn pwm output frequency = (f sys /4) / (2256) = f sys /2048 = 7.8125 khz, duty = 128/(2256)= 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ? 16-bit stm, pwm mode, edge-aligned mode, tndpx=1 ccrp 1~255 0 pe ? iod ccra duty ccrp ? 56 65536 the pwm output period is determined by the ccra register value together wi th the t m clock while the pw m d uty c ycle i s d efned b y t he ( ccrp256) v alue e xcept wh en t he c crp v alue i s e qual t o 0 .
rev. 1.00 96 ??to?e? 01? ?01? rev. 1.00 97 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom counte? value ccrp ccra tn?n tnpau tnp?l ccrp int . flag tnpf ccra int . flag tnaf tmn ? / p pin ( tn ?c =1) time counte? ?lea?ed ?y ccrp pause resume counte? stop if tn?n ?it low counte? reset when tn?n ?etu?ns high tndpx = 0; tnm [1:0] = 10 pwm duty cy?le set ?y ccra pwm ?esumes ope?ation ?utput ?ont?olled ?y othe? pin-sha?ed fun?tion ?utput inve?ts when tnp?l = 1 pwm pe?iod set ?y ccrp tmn ? / p pin ( tn ?c =0) pwm output mode C tndxp = 0 note: 1. here tndpx=0 C counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n = 0 for ht66f0185 only
rev. 1.00 98 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 99 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom counte? value ccrp ccra tn?n tnpau tnp?l ccrp int . flag tnpf ccra int . flag tnaf tmn ? / p pin ( tn ?c =1) time counte? ?lea?ed ?y ccra pause resume counte? stop if tn?n ?it low counte? reset when tn?n ?etu?ns high tndpx = 1; tnm [1:0] = 10 pwm duty cy?le set ?y ccrp pwm ?esumes ope?ation ?utput ?ont?olled ?y othe? pin-sha?ed fun?tion ?utput inve?ts when tnp?l = 1 pwm pe?iod set ?y ccra tmn ? / p pin ( tn ?c =0) pwm output mode C tndxp = 1 note: 1. here tndpx=1 C counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n = 0 for ht66f0185 only
rev. 1.00 98 ??to?e? 01? ?01? rev. 1.00 99 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom single pulse output mode to se lect t his mode , bit s t nm1 and t nm0 i n t he t mnc1 regi ster should be se t t o 10 respe ctively and also the tnio1 and tnio0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the tmn output pin. the trigger for the pulse output lead ing edge is a low to high transition of the tnon bit, which can be implemented using the application program. however in the single pulse mode, the tnon bit can also be made to automatically change from low to high using the external tckn pin, which will in turn initiate the single pulse output. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a tmn interrupt. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr and tndpx bits are not used in this mode. tn?n ?it 0 1 s/w command settn?n o? tckn pin t?ansition tn?n ?it 1 0 ccra t?ailing edge s/w command clrtn?n o? ccra compa?e mat?h tpn ?utput pin pulse width = ccra value ccra leading edge single pulse generation
rev. 1.00 100 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 101 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom counte? value ccrp ccra tn?n tnpau tnp?l ccrp int. flag tnpf ccra int. flag tnaf tmn ?/p pin (tn?c=1) time counte? stopped ?y ccra pause resume counte? stops ?y softwa?e counte? reset when tn?n ?etu?ns high tnm [1:0] = 10 ; tni? [1:0] = 11 pulse width set ?y ccra ?utput inve?ts when tnp?l = 1 no ccrp inte??upts gene?ated tmn ?/p pin (tn?c=0) tckn pin softwa?e t?igge? clea?ed ?y ccra mat?h tckn pin t?igge? auto. set ?y tckn pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high. 5. in the single pulse mode, tnio [1:0] must be set to 11 and can not be changed. 6. n = 0 for ht66f0185 only
rev. 1.00 100 ??to?e? 01? ?01? rev. 1.00 101 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom capture input mode to s elect this mode bits tnm1 and tnm0 in the tm nc1 regis ter s hould be s et to 01 res pectively. this mode enables external s ignals to capture and s tore the pres ent value of the internal counter and c an t herefore be use d fo r a pplications suc h a s pu lse wi dth m easurements. t he e xternal si gnal is supplied on the tpn pin, whose active edge can be a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the tnio1 and tnio0 bits in the tmnc1 register . the counter is started when the tnon bit changes from low to high which is initiated using the application program. when t he r equired e dge t ransition a ppears o n t he t pn p in t he p resent v alue i n t he c ounter wi ll b e latched into the ccra registers and a tmn interrupt generated. irrespective of what events occur on the tpn pin the counter will continu e to free run until the tnon bit changes from high to low . when a ccrp c ompare m atch oc curs t he c ounter wi ll re set ba ck t o z ero; i n t his wa y t he ccrp va lue can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p , a tmn interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the tnio1 and tnio0 bits can select the active trigger edge on the tpn pin to be a rising edge, falling edge or both edge types. if the tnio1 and tnio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpn pin, however it must be noted that the counter will continue to run. the tncclr and tndpx bits are not used in this mode.
rev. 1.00 10 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 103 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom counte? value yy ccrp tn?n tnpau ccrp int. flag tnpf ccra int. flag tnaf ccra value time counte? ?lea?ed ?y ccrp pause resume counte? reset tnm [1:0] = 01 tmn ?aptu?e pin tpn xx counte? stop tni? [1:0] value xx yy xx yy a?tive edge a?tive edge a?tive edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disa?le captu?e capture input mode note: 1. tnm [1:0] = 01 and active edge set by the tnio [1:0] bits 2. a tmn capture input pin active edge transfers the counter value to ccra 3. tncclr bit not used 4. no output function -- tnoc and tnpol bits are not used 5. ccrp determin es the counter value and the counter has a maximum count value when ccrp is equal to zero. 6. n = 0 for ht66f0185 only
rev. 1.00 10? ??to?e? 01? ?01? rev. 1.00 103 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom periodic type tm C ptm the pe riodic t ype t m c ontains fv e o perating m odes, wh ich a re c ompare ma tch ou tput, t imer/ event counter , capture input, single pulse output and pwm output modes. the periodic tm can also be controlled with one external input pin and can drive one external output pin. device tm core tm no. tm input pin tm output pin HT66F0175 10- ? it ptm tm0 ? tm1 tck0 ? tck1 tp0 ? tp1 ht66f0185 10- ? it ptm tm1 tck1 tp1 f sys f sys /? f h /6? f h /16 f tbc tckn 000 001 010 011 100 101 110 111 tnck?~tnck0 10-?it count-up counte? 10-?it compa?ato? p ccrp ?0~?9 ?0~?9 10-?it compa?ato? a tn?n tnpau compa?ato? a mat?h compa?ato? p mat?h counte? clea? 0 1 ?utput cont?ol pola?ity cont?ol pin cont?ol tpn tn?c tnm1? tnm0 tni?1? tni?0 tnaf inte??upt tnpf inte??upt tnp?l tncp ccra tncclr edge dete?to? tni?1? tni?0 f h /8 1 0 tncapts periodic type tm block diagram C n = 0 or 1 periodic tm operation the size of periodic tm is 16-bit wide and its core is a 10-bit count-up counter which is driven by a user selectable internal or externa l clock source. there are also two internal comparators with the names, comparato r a and comparator p . these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp and ccra comparators are 10-bit wide whose value is respectively compared with all counter bits. the onl y wa y of c hanging t he va lue of t he 10-bi t c ounter usi ng t he a pplication program i s t o clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the periodic type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control the output pins. all operating setup conditions are selected using relevant internal registers.
rev. 1.00 10 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 105 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom periodic type tm register description overall operation of the periodic tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra and ccrp value. the remaining two registers are control registers which setup the different operating and control modes. register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tmnc0 tnpau tnck ? tnck1 tnck0 tn ? n tmnc1 tnm1 tnm0 tni ? 1 tni ? 0 tn ? c tnp ? l tncapts tncclr tmndl d7 d6 d5 d ? d3 d ? d1 d0 tmndh d9 d8 tmnal d7 d6 d5 d ? d3 d ? d1 d0 tmnah d9 d8 tmnrpl tnrp7 tnrp6 tnrp5 tnrp ? tnrp3 tnrp ? tnrp1 tnrp0 tmnrph tnrp9 tnrp8 periodic tm registers list C n = 0 or 1 tmndl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d ? d3 d ? d1 d0 r/w r r r r r r r r p ? r 0 0 0 0 0 0 0 0 bit 7~0 tmn counter low byte register bit 7 ~ bit 0 tmn 10-bit counter bit 7 ~ bit 0 tmndh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r p ? r 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tmn counter high byte register bit 1 ~ bit 0 tmn 10-bit counter bit 9 ~ bit 8 tmnal register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 0 bit 7~0 tmn ccra low byte register bit 7 ~ bit 0 tmn 10-bit ccra bit 7 ~ bit 0
rev. 1.00 10? ??to?e? 01? ?01? rev. 1.00 105 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom tmnah register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w p ? r 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tmn ccra high byte register bit 1 ~ bit 0 tmn 10-bit ccra bit 9 ~ bit 8 tmnrpl register bit 7 6 5 4 3 2 1 0 name tnrp7 tnrp6 tnrp5 tnrp ? tnrp3 tnrp ? tnrp1 tnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 0 bit 7~0 tnrp7~ptnrp0 : tmn ccrp low byte register bit 7 ~ bit 0 tmn 10-bit ccrp bit 7 ~ bit 0 tmnrph register bit 7 6 5 4 3 2 1 0 name tnrp9 tnrp8 r/w r/w r/w p ? r 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tnrp9~tnrp8 : tmn ccrp high byte register bit 1 ~ bit 0 tmn 10-bit ccrp bit 9 ~ bit 8
rev. 1.00 106 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 107 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom tmnc0 register bit 7 6 5 4 3 2 1 0 name tnpau tnck ? tnck1 tnck0 tn ? n r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 bit 7 tnpau : tmn counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tmn will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0 : select tmn counter clock 000: f /4 001: f 010: f h /16 011: f h /64 100: f tbc 101: f h /8 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tmn. the external pin clock source can be chosen to be active on the rising or falling edge. the cloc k source f is the system clock, while f h and f tbc are other internal clocks, the detai ls of which can be found in the oscillator section. bit 3 tnon : tmn counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tmn. setting the bit high enables the counter to run while clearing the bit disables the tmn. clearing this bit to zero will stop the counter from counting and turn of f the tmn which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. if the tmn is in the compare match output mode then the tmn output pin will be reset to its initial condition, as specifed by the tnoc bit, when the tnon bit changes from low to high. bit 2~0 unimplemented, read as 0
rev. 1.00 106 ??to?e? 01? ?01? rev. 1.00 107 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom tmnc1 register bit 7 6 5 4 3 2 1 0 name tnm1 tnm0 tni ? 1 tni ? 0 tn ? c tnp ? l tncapts tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 0 bit 7~6 tnm1~tnm0 : select tmn operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these b its se tup t he r equired o perating m ode f or t he t mn. t o e nsure r eliable o peration the tmn should be switched of f before any changes are made to the tnm1 and tnm0 bits. in the t imer/counter mode, the tmn output pin control will be disabled. bit 5~4 tnio1~tnio0 : select tmn external pin tpn function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm output mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tpn or tckn 01: input capture at falling edge of tpn or tckn 10: input capture at rising/falling edge of tpn or tckn 11: input capture disabled timer/counter mode unused these two bits are used to determine how the tmn output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tmn is running. in t he com pare ma tch out put mode , t he t nio1 a nd t nio0 bi ts de termine how t he tmn output pin changes state when a compare match occurs from the comparator a. the t mn ou tput pi n c an be se tup t o swi tch hi gh, swi tch l ow or t o t oggle i ts pr esent state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tmn output pin should be setup using the tnoc bit in the tmnc1 register . note that the output level requested by the tnio1 and tnio0 bits must be dif ferent from the initial value setup using the tnoc bit otherwise no change will occur on the tmn output pin when a compare match occurs. after the tmn output pin changes state, it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm mode, the tnio1 and tnio0 bits determine how the tmn output pin changes state when a certain compare match condition occurs. the tmn output function i s m odified b y c hanging t hese t wo b its. i t i s n ecessary t o o nly c hange t he values of t he t nio1 a nd t nio0 bi ts onl y a fter t he t mn ha s be en swi tched of f. unpredictable pwm outputs will occur if the t nio1 and t nio0 bits are changed when the tmn is running.
rev. 1.00 108 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 109 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom bit 3 tnoc : tmn tpn output control compare match output mode 0: initial low 1: initial high pwm output mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tmn output pin. its operation depends upon whether t mn is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no ef fect if the tmn is in the t imer/counter mode. in the compare match output mode it determines the logic level of the tmn output pin before a compare match occurs. in the pwm mode/single pulse output mode it determines if the pwm signal is active high or active low. bit 2 tnpol : tmn tpn output polarity control 0: non-inverted 1: inverted this bit controls the polarity of the tpn output pin. when the bit is set high the tmn output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the tmn is in the t imer/counter mode. bit 1 tncapts : tmn capture t rigger source selection 0: from tpn pin 1: from tckn pin bit 0 tncclr : tmn counter clear condition selection 0: comparator p match 1: comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he periodic t m c ontains t wo c omparators, com parator a a nd com parator p , e ither of which can be selected to clear the internal counter . w ith the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm output, single pulse output or capture input mode.
rev. 1.00 108 ??to?e? 01? ?01? rev. 1.00 109 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom periodic type tm operation modes the periodic t ype tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the tncclr bit is low , there are two ways in which the counter can be cleared. one is when a c ompare m atch f rom c omparator p , t he o ther i s wh en t he c crp b its a re a ll z ero wh ich a llows the c ounter t o ove rfow. he re bot h t naf a nd t npf i nterrupt re quest fa gs for com parator a a nd comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr i s h igh n o t npf i nterrupt r equest fa g wi ll b e g enerated. i n t he c ompare ma tch ou tput mode, the ccra can not be set to 0. as t he n ame o f t he m ode su ggests, a fter a c omparison i s m ade, t he t mn o utput p in wi ll c hange state. the tmn output pin condition however only changes state when a tnaf interrupt request fag is generated after a compare match occurs from comparator a. the tnpf interrupt request fag, generated from a compare match occurs from comparator p , will have no ef fect on the tmn output pin. the way in which the tmn output pin changes state are determined by the condition of the tnio1 and tnio0 bits in the tmnc1 register . the tmn output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tmn output pin, which is setup after the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place.
rev. 1.00 110 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 111 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom counte? value 0x3ff ccrp ccra tn?n tnpau tnp?l ccrp int. flag tnpf ccra int. flag tnaf tmn ?/p pin time ccrp=0 ccrp > 0 counte? ove?flow ccrp > 0 counte? ?lea?ed ?y ccrp value pause resume stop counte? resta?t tncclr = 0; tnm [1:0] = 00 ?utput pin set to initial level low if tn?c=0 ?utput toggle with tnaf flag note tni? [1:0] = 10 a?tive high ?utput sele?t he?e tni? [1:0] = 11 toggle ?utput sele?t ?utput not affe?ted ?y tnaf flag. remains high until ?eset ?y tn?n ?it ?utput pin reset to initial value ?utput ?ont?olled ?y othe? pin-sha?ed fun?tion ?utput inve?ts when tnp?l is high compare match output mode C tncclr = 0 note: 1. w ith tncclr=0, a comparator p match will clear the counter 2. the tmn output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. n = 0 or 1 for HT66F0175 while n = 1 for ht66f0185
rev. 1.00 110 ??to?e? 01? ?01? rev. 1.00 111 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom counte? value 0x3ff ccrp ccra tn?n tnpau tnp?l ccrp int. flag tnpf ccra int. flag tnaf tmn ?/p pin time ccra=0 ccra = 0 counte? ove?flow ccra > 0 counte? ?lea?ed ?y ccra value pause resume stop counte? resta?t tncclr = 1; tnm [1:0] = 00 ?utput pin set to initial level low if tn?c=0 ?utput toggle with tnaf flag note tni? [1:0] = 10 a?tive high ?utput sele?t he?e tni? [1:0] = 11 toggle ?utput sele?t ?utput not affe?ted ?y tnaf flag. remains high until ?eset ?y tn?n ?it ?utput pin reset to initial value ?utput ?ont?olled ?y othe? pin-sha?ed fun?tion ?utput inve?ts when tnp?l is high tnpf not gene?ated no tnaf flag gene?ated on ccra ove?flow ?utput does not ?hange compare match output mode - tncclr = 1 note: 1. w ith tncclr=1, a comparator a match will clear the counter 2. the tmn output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. a tnpf fag is not generated when tncclr =1 5. n = 0 or 1 for HT66F0175 while n = 1 for ht66f0185
rev. 1.00 11 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 113 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tmn output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tmn output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to se lect t his mode , bit s t nm1 and t nm0 i n t he t mnc1 regi ster should be se t t o 10 respe ctively and also the tnio1 and tnio0 bits should be set to 10 respectively . the pwm function within the t mn i s use ful for a pplications whi ch re quire func tions suc h a s m otor c ontrol, he ating c ontrol, illumination control, etc. by providing a signal of fxed frequency but of varying duty cycle on the tmn output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pw m m ode, t he t ncclr bi t ha s no e ffect a s t he pw m period. both of the ccrp and ccra registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycl e. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tmn output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. ? 10-bit ptm, pwm mode, ccrp 1~1023 0 pe ? iod 1~10 ? 3 10 ?? duty ccra if f sys =16mhz, tm clock source select f sys /4, ccrp=512 and ccra=128, the tmn pwm output frequency = (f sys /4)/512 = f sys /2048 = 7.8125khz, duty=128/512=25%, if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%.
rev. 1.00 11 ? ??to?e? 01? ?01? rev. 1.00 113 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom counte? value ccrp ccra tn?n tnpau tnp?l ccrp int. flag tnpf ccra int. flag tnaf tmn ?/p pin (tn?c=1) time counte? ?lea?ed ?y ccrp pause resume counte? stop if tn?n ?it low counte? reset when tn?n ?etu?ns high tnm [1:0] = 10 pwm duty cy?le set ?y ccra pwm ?esumes ope?ation ?utput ?ont?olled ?y othe? pin-sha?ed fun?tion ?utput inve?ts when tnp?l = 1 pwm pe?iod set ?y ccrp tmn ?/p pin (tn?c=0) pwm mode note: 1. the counter is cleared by ccrp. 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n = 0 or 1 for HT66F0175 while n = 1 for ht66f0185
rev. 1.00 11 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 115 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom single pulse output mode to se lect t his mode , bit s t nm1 and t nm0 i n t he t mnc1 regi ster should be se t t o 10 respe ctively and also the tnio1 and tnio0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the tmn output pin. the trigger for the pulse output lead ing edge is a low to high transition of the tnon bit, which can be implemented using the application program. however in the single pulse mode, the tnon bit can also be made to automatically change from low to high using the external tckn pin, which will in turn initiate the single pulse output. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a tmn interrupt. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr is not used in this mode. tn?n ?it 0 1 s/w command settn?n o? tckn pin t?ansition tn?n ?it 1 0 ccra t?ailing edge s/w command clrtn?n o? ccra compa?e mat?h tpn ?utput pin pulse width = ccra value ccra leading edge single pulse generation
rev. 1.00 11 ? ??to?e? 01? ?01? rev. 1.00 115 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom counte? value ccrp ccra tn?n tnpau tnp?l ccrp int. flag tnpf ccra int. flag tnaf tmn ?/p pin (tn?c=1) time counte? stopped ?y ccra pause resume counte? stops ?y softwa?e counte? reset when tn?n ?etu?ns high tnm [1:0] = 10 ; tni? [1:0] = 11 pulse width set ?y ccra ?utput inve?ts when tnp?l = 1 no ccrp inte??upts gene?ated tmn ?/p pin (tn?c=0) tckn pin softwa?e t?igge? clea?ed ?y ccra mat?h tckn pin t?igge? auto. set ?y tckn pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high. 5. in the single pulse mode, tnio [1:0] must be set to 11 and can not be changed. 6. n = 0 or 1 for HT66F0175 while n = 1 for ht66f0185
rev. 1.00 116 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 117 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom capture input mode to s elect this mode bits tnm1 and tnm0 in the tm nc1 regis ter s hould be s et to 01 res pectively. this mode enables external s ignals to capture and s tore the pres ent value of the internal counter and can therefore be used for applic ations such as pulse width measurements. the external signal is supplied on the tpn or tckn pin, selected by the tncapts bit in the tmnc1 register . the input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the tnio1 and tnio0 bits in the tmnc1 register . the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpn or tckn pin the present value in the counter will be latched into the ccra registers and a tmn interrupt generated. irrespective of what events occur on the tpn or tckn pin the counter will continue to free run until the tnon bit changes from high to low . when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a tmn interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the tnio1 and tnio0 bits can select the active trigger edge on the tpn or tckn pin to be a rising edge, falling edge or both edge types. if the tnio1 and tnio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpn or tckn pin, however it must be noted that the counter will continue to run. as the tpn or tckn pin is pin shared with other functions, care must be taken if the tmn is in the input capture mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the tncclr, tnoc and tnpol bits are not used in this mode.
rev. 1.00 116 ??to?e? 01? ?01? rev. 1.00 117 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom counte? value yy ccrp tn?n tnpau ccrp int. flag tnpf ccra int. flag tnaf ccra value time counte? ?lea?ed ?y ccrp pause resume counte? reset tnm [1:0] = 01 tmn ?aptu?e pin tpn o? tckn xx counte? stop tni? [1:0] value xx yy xx yy a?tive edge a?tive edge a?tive edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disa?le captu?e capture input mode note: 1. tnm [1:0] = 01 and active edge set by the tnio [1:0] bits 2. a tmn capture input pin active edge transfers the counter value to ccra 3. tncclr bit not used 4. no output function C tnoc and tnpol bits are not used 5. ccrp determin es the counter value and the counter has a maximum count value when ccrp is equal to zero. 6. n = 0 or 1 for HT66F0175 while n = 1 for ht66f0185
rev. 1.00 118 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 119 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however , to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller , the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview these devices contain a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. it also can convert the internal signals, such as the bandgap reference voltage, into a 12-bit digital value. the external or internal analog signal to be converted is determined by the sains2~sains0 bits together with the sacs2~sacs0 bits. note that when the external and internal analog signals are simultaneously selected to be converted, the internal analog signal will have the priority . in the meantime the external analog signal will temporarily be switched off unt il t he i nternal a nalog si gnal i s de selected. more de tailed i nformation a bout t he a/ d i nput signal i s d escribed i n t he a/d c onverter c ontrol r egisters a nd a/d c onverter in put si gnal sections respectively. the accompanyin g block diagram shows the internal structure of the a/d converter together with its associated registers. device external input channel internal analog signals a/d signal select bits HT66F0175 an0~an7 v dd ? v dd / ?? v dd / ?? v r ? v r / ?? v r / ? sains ? ~sains0; sacs ? ~sacs0 ht66f0185 an0~an7 v dd ? v dd / ?? v dd / ?? v r ? v r / ?? v r / ? sains ? ~sains0; sacs ? ~sacs0 ace7~ace0 sacs?~sacs0 sains?~sains0 a/d conve?te? start adbz adcen v ss a/d clo?k ? n (n=0~7) f sys sacks?~ sacks0 v dd adcen sad?l sad?h an0 an1 an7 a/d refe?en?e voltage a/d data registe?s v dd v dd /? v dd /? v r v r /? v r /? adrfs pga v ri v refi v bg (gain=1~?) savrs3~savrs0 adpgaen v ref v r v dd vrefps vrefips a/d converter structure
rev. 1.00 118 ??to?e? 01? ?01? rev. 1.00 119 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom a/d converter register description overall operation of the a/d converter is controlled using six registers. a read only register pair exists to store the a/d converter data 12-bit value. one register , acerl, is used to confgure the external analog input pin function. the remaining three registers are control registers which setup the operating and control function of the a/d converter. register name bit 7 6 5 4 3 2 1 0 sad ? l (adrfs=0) d3 d ? d1 d0 sad ? l (adrfs=1) d7 d6 d5 d ? d3 d ? d1 d0 sad ? h (adrfs=0) d11 d10 d9 d8 d7 d6 d5 d ? sad ? h (adrfs=1) d11 d10 d9 d8 sadc0 start adbz adcen adrfs sacs ? sacs1 sacs0 sadc1 sains ? sains10 sains0 sacks ? sacks1 sacks0 sadc ? adpgaen vbgen vrefips vrefps savrs3 savrs ? savrs1 savrs0 acerl ace7 ace6 ace5 ace ? ace3 ace ? ace1 ace0 a/d converter registers list a/d converter data registers C sadol, sadoh as these devices contain an internal 12-bit a/d converter , it requires two data registers to store the converted value. these are a high byte register , known as sadoh, and a low byte register , known as sadol. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is ut ilised, t he form at i n whi ch t he da ta i s st ored i s c ontrolled by t he adrfs bi t i n t he sadc0 register as shown in the accompany ing table. d0~d1 1 are the a/d conversion result data bits. any unused bits will be read as zero. the a/d data registers contents will keep unchanged if the a/d converter is disabled. adrfs sadoh sadol 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d7 d6 d5 d ? d3 d ? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d7 d6 d5 d ? d3 d ? d1 d0 a/d converter data registers
rev. 1.00 1 ? 0 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 1?1 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom a/d converter control registers C sadc0, sadc1, sadc2, acerl to control the function and operation of the a/d converter, three control registers known as sadc0, sadc1 and sadc2 are provided. these 8-bit registers defne functions such as the selection of which analog channel is connected to the internal a /d converter , the digitis ed data format, the a / d clock source as well as controlling the start function and monitoring the a/d converter busy status. as these devices contain only one actual analog to digital converter hardware circuit, each of the external and internal analog signals must be routed to the converter . the sacs2~sacs0 bits i n t he sadc 0 re gister a re use d t o de termine whi ch e xternal c hannel i nput i s se lected t o be converted. the sains2~sains0 bits in the sadc1 register are used to determine that the analog signal to be converted comes from the internal analog signal or external analog channel input. if the sains2~sains0 bits are set to 000 or 100, the external analog channel input will be selected to be converted and the sa cs2~sacs0 bits can deternine w hich external channel is s elected to be converted. if the sains2~sains0 bits are set to any other values except 000 and 100, one of the internal analog signals can be selected to be converted. the internal analog signals can be de rived fr om t he a/ d c onverter su pply p ower, vdd, o r i nternal r eference v oltage, vr , wi th a specifc ratio of 1, 1/2 or 1/4. if the internal analog signal is selected to be converted, the external channel signal input will automatically be switched off to avoid the signal contention. sains [2:0] sacs [2:0] input signals description 000 ? 100 000~111 an0~an7 exte ? nal ? hannel analog input 001 xxx v dd a/d ? onve ? te ? powe ? supply voltage 010 xxx v dd / ? a/d ? onve ? te ? powe ? supply voltage/ ? 011 xxx v dd / ? a/d ? onve ? te ? powe ? supply voltage/ ? 101 xxx v r inte ? nal ? efe ? en ? e voltage 110 xxx v r / ? inte ? nal ? efe ? en ? e voltage/ ? 111 xxx v r / ? inte ? nal ? efe ? en ? e voltage/ ? a/d converter input signal selection the analog input pin function s election bits in the a cerl regis ter determine w hich pins on i/o ports are used as external analog channels for the a/d converter input and which pins are not to be used as the a/d converter input. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin-shared functions will be removed. in addition, any internal pull- high resistor connected to the pin will be automatically removed if the pin is selected to be an a/d converter input.
rev. 1.00 1?0 ??to?e? 01? ?01? rev. 1.00 1 ? 1 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom ? sadc0 register bit 7 6 5 4 3 2 1 0 name start adbz adcen adrfs sacs ? sacs1 sacs0 r/w r/w r r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 bit 7 start : start the a/d conversion 010: start this bit is used to initiate an a/ d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. bit 6 adbz : a/d converter busy fag 0: no a/d conversion is in progress 1: a/d conversion is in progress this read only fag is us ed to indicate w hether the a /d convers ion is in progress or not. when the st art bit is set from low to high and then to low again, the adbz fag will be set to 1 to indicate that the a/d conversion is initiated. the adbz fag will be cleared to 0 after the a/d conversion is complete. bit 5 adcen : a/d converter function enable control 0: disable 1: enable this bit controls the a/d internal function. this bit should be set to one to enable the a/ d c onverter. if t he bi t i s se t l ow, t hen t he a/ d c onverter wi ll be swi tched of f reducing the device power consumption. when the a/d converter function is disabled, the contents of the a/d data register pair, sadoh/sadol, will keep unchanged. bit 4 adrfs : a/d conversion data format select 0: a/d converter data format sadoh = d [11:4]; sadol = d [3:0] 1: a/d converter data format sadoh = d [11:8]; sadol = d [7:0] this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d converter data register section. bit 3 unimplemented, read as 0 bit 2~0 sacs2~sacs0 : a/d converter external analog input channel select 000: an0 001: an1 010: an2 011: an3 100: an4 101: an5 110: an6 111: an7
rev. 1.00 1 ?? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 1?3 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom ? sadc1 register bit 7 6 5 4 3 2 1 0 name sains ? sains10 sains0 sacks ? sacks1 sacks0 r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 bit 7~5 sains2~sains0 : a/d converter input signal select 000, 100: external signal C external analog channel input 001: internal signal C internal a/d converter power supply voltage v 010: internal signal C internal a/d converter power supply voltage v /2 011: internal signal C internal a/d converter power supply voltage v /4 101: internal signal C internal reference voltage v r 110: internal signal C internal reference voltage v r /2 111: internal signal C internal reference voltage v r /4 when the internal analog signal is selected to be converted, the externa l channel input signal will automatically be switched of f regardless of the sacs2~sacs0 bit feld value. the internal reference voltage can be derived from various sources selected using the savrs 3~savrs0 bits in the sadc2 register. bit 4~3 unimplemented, read as 0 bit 2~0 sacks2~sacks0 : a/d conversion clock source select 000: f 001: f /2 010: f /4 011: f /8 100: f /16 101: f /32 110: f /64 111: f /128 these bits are used to select the clock source for the a/d converter.
rev. 1.00 1?? ??to?e? 01? ?01? rev. 1.00 1 ? 3 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom ? sadc2 register bit 7 6 5 4 3 2 1 0 name adpgaen vbgen vrefips vrefps savrs3 savrs ? savrs1 savrs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 0 bit 7 adpgaen : a/d converter pga function enable control 0: disable 1: enable this bit controls the internal pga function to provide various reference voltage for the a/d converter . when the bit is set high, the internal reference voltage, v r , can be used as the internal converted signal or reference voltage by the a/d converter . if the internal reference voltage is not used by the a/d converter , then the pga function should be properly confgured to conserve power. bit 6 vbgen : internal bandgap reference voltage enable control 0: disable 1: enable this bit controls the internal bandgap circuit on/of f function to the a/d converter . when the bit is set high, the bandgap reference voltage can be used by the a/d converter. if the bandgap reference voltage is not used by the a/d converter and the l vd or l vr function is disabled, then the bandgap reference circuit will be automatically s witched of f to conserve pow er. when the bandgap reference voltage is switched on for use by the a/d converter , a time, t bgs , should be allowed for the bandgap circuit to stabilise before implementing an a/d conversion. bit 5 vrefips : vrefi pin selection bit 0: disable C vrefi pin is not selected 1: enable C vrefi pin is selected bit 4 vrefps : vref pin selection bit 0: disable C vref pin is not selected 1: enable C vref pin is selected bit 3~0 savrs3~savrs0 : a/d converter reference voltage select 0000: v 0001: v refi 0010: v refi 2 0011: v refi 3 0100: v refi 4 1001: reserved, can not be used. 1010: v bg 2 1011: v bg 3 1100: v bg 4 others: v when the a/d converter reference voltage source is selected to derive from the internal vbg voltage, the reference voltage which comes from the external vdd or vrefi pin will be automatically switched off.
rev. 1.00 1 ?? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 1?5 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom ? acerl register bit 7 6 5 4 3 2 1 0 name ace7 ace6 ace5 ace ? ace3 ace ? ace1 ace0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 1 1 1 1 1 1 1 1 bit 7 ace7 : defne pb3 is a/d input or not 0: not a/d input 1: a/d input, an7 bit 6 ace6 : defne pa7 is a/d input or not 0: not a/d input 1: a/d input, an6 bit 5 ace5 : defne pa6 is a/d input or not 0: not a/d input 1: a/d input, an5 bit 4 ace4 : defne pa5 is a/d input or not 0: not a/d input 1: a/d input, an4 bit 3 ace3 : defne pa4 is a/d input or not 0: not a/d input 1: a/d input, an3 bit 2 ace2 : defne pb2 is a/d input or not 0: not a/d input 1: a/d input, an2 bit 1 ace1 : defne pb1 is a/d input or not 0: not a/d input 1: a/d input, an1 bit 0 ace0 : defne pb0 is a/d input or not 0: not a/d input 1: a/d input, an0
rev. 1.00 1?? ??to?e? 01? ?01? rev. 1.00 1 ? 5 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom a/d input pins all of the a /d analog input pins are pin-shared w ith the i/o pins as w ell as other functions . the corresponding pin-s hared function s election bits in the a cerl register determine w hich external input pins are selected as a/d converter analog channel inputs or other functional pins. if the corresponding pin is setup to be an a/d converter analog channel input, the original pin functions will be di sabled. in t his wa y, pi ns c an be c hanged un der pr ogram c ontrol t o c hange t heir fu nction between a/d inputs and other functions. all pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the port control register to enable the a/d input as when the relevant a/d input function selection bits enable an a/d input, the status of the port control register will be overridden. the a/d converter has its own reference voltage input pin, vrefi. however , the reference voltage can a lso b e su pplied fr om t he po wer su pply pi n o r a n i nternal b andgap c ircuit, a c hoice wh ich i s made through the savrs3~savrs0 bits in the sadc2 register. the selected a/d reference voltage can be output on the v ref pin. the analog input values must not be allow ed to exceed the value of vref . note that the vrefi or vref pin function selection bit in the sadc2 register must be properly confgured before the reference voltage pin function is used. a/d reference voltage the reference voltage supply to the a/d converter can be supplied from the positive power supply pin, v dd , an external reference source supplied on pin vrefi or an internal reference source derived from the bandgap circuit. then the s elected reference voltage s ource can be amplif ed through a programmable gain amplifer except the voltage sourced from v dd . the pga gain can be equal to 1, 2, 3 or 4. the desired selection is made using the sa vrs3~savrs0 bits in the sadc2 register and relevant pin-shared function selection bits. note that the desired selected reference voltage will be output on the vref pin which is pin-shared with other functions. as the vrefi and vref pins both are pin-shared with other functions, when the vrefi or vref pin is selected as the reference voltage supply pi n, t he vrefi or vref pi n-shared func tion se lection bi t should be prope rly confgured to disable other pin-shared functions. a/d operation the st art bit in the sadc0 register is used to start the ad conversion. when the microcontroller sets t his b it f rom l ow t o h igh a nd t hen l ow a gain, a n a nalog t o d igital c onversion c ycle wi ll b e initiated. the adbz bi t i n t he sadc0 re gister i s use d t o i ndicate whe ther t he a nalog t o di gital c onversion process is in progress or not. this bit will be automatically set to 1 by the microcontroller after an a/d conversion is successfully initiated. when the a/d conversion is complete, the adbz will be cleared to 0. in addition, the corresponding a/d interrupt request fag will be set in the interrupt control register , and if the corresponding interrupt control bits are enabled, an internal interrupt signal wil l be generated. thi s a/ d i nternal int errupt si gnal wi ll direct the progra m flow t o t he associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can poll the adbz bit in the sadc0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle.
rev. 1.00 1 ? 6 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 1?7 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom the clock source for the a/d converter , which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys . the division ratio value is determined by the sacks2~sacks0 bits in the sadc1 register . although the a/d cloc k source is determined by the system clock f sys and by bits sacks2~sacks0, there are some limitations on the maximum a/d clock source speed that can be selected. as the recommended range of permissible a/d clock period, t adck , is from 0.5s to 10, care must be taken for system clock frequencies. for example, as the system clock operates at a frequency of 8mhz, the sacks2~sacks0 bits should not be set to 000, 001 or 1 11. doing so will give a/d clock periods that are less than the minimum a/d clock period which m ay re sult i n i naccurate a/ d c onversion va lues. re fer t o t he fol lowing t able for e xamples, where values marked with an asteri sk * show where, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period. f sys a/d clock period (t adck ) sacks[2:0] = 000 (f sys ) sacks[2:0] = 001 (f sys /2) sacks[2:0] = 010 (f sys /4) sacks[2:0] = 011 (f sys /8) sacks[2:0] = 100 (f sys /16) sacks[2:0] = 101 (f sys /32) sacks[2:0] = 110 (f sys /64) sacks[2:0] = 111 (f sys /128) 1 mhz 1s 2s 4s 8s 16s * 32s * 64s * 128s * ? mhz 500ns 1s 2s 4s 8s 16s * 32s * 64s * ? mhz 250ns * 500ns 1s 2s 4s 8s 16s * 32s * 8 mhz 125ns * 250ns * 500ns 1s 2s 4s 8s 16s * 1 ? mhz 83ns * 167ns * 333ns * 667ns 1.33s 2.67s 5.33s 10.67s * 16 mhz 62.5ns * 125ns * 250ns * 500ns 1s 2s 4s 8s ? 0 mhz 50ns * 100ns * 200ns * 400ns * 800ns 1.6s 3.2s 6.4s a/d clock period examples controlling t he powe r on/ off func tion of t he a/ d c onverter c ircuitry i s i mplemented usi ng t he adcen bit in the sadc0 register . this bit must be set high to power on the a/d converter . when the adcen bit is set high to power on the a/d converter internal circuitry , a certain delay , as indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs, if the adcen bit is high, then some power will still be consumed. in power conscious applications it is therefore recommended that the adcen is set low to reduce power consumption when the a/d converter function is not being used. conversion rate and timing diagram a com plete a/d conversi on contains two parts, dat a sampli ng and dat a conversi on. the dat a sampling which is defned as t ads takes 4 a/d clock cycles and the data conversion takes 12 a/d clock cycles. t herefore a total of 16 a/ d clock cycles for an a/ d conversion which is defned as t adc are necessary. maximum single a/d conversion rate = a/d clock period / 16 (1) the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware w ill begin to carry out the conversion, d uring wh ich t ime t he p rogram c an c ontinue wi th o ther f unctions. t he t ime t aken f or t he a/d conversion is 16 t adck clock cycles where t adck is equal to the a/d clock period.
rev. 1.00 1?6 ??to?e? 01? ?01? rev. 1.00 1 ? 7 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom adcen start adbz sacs[?:0] off on off on t ?n?st t ads a/d sampling time t ads a/d sampling time sta?t of a/d ?onve?sion sta?t of a/d ?onve?sion sta?t of a/d ?onve?sion end of a/d ?onve?sion end of a/d ?onve?sion t adc a/d ?onve?sion time t adc a/d ?onve?sion time t adc a/d ?onve?sion time 011b 010b 000b 001b a/d ?hannel swit?h (sains =000b) a/d conversion timing summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/ d conversion process. step 1 select the require d a/d conversion clock by properly programming the sacks2~sacks0 bits in the sadc1 register. step 2 enable the a/d converter by setting the adcen bit in the sadc0 register to one. step 3 select which signal is to be connected to the internal a/d converter by correctly confguring the sains2~sains0 bits select the external channel input to be converted, go to step 4. select the internal analog signal to be converted, go to step 5. step 4 if the a/d input signal comes from the external channel input selectin g by confguring the sains bit feld, the corresponding pins should frst be confgured as a/d input function by confguring the relevant pi n-shared fu nction c ontrol bi ts. t he de sired a nalog c hannel t hen shou ld be se lected by confguring the sacs bit feld. after this step, go to step 6. step 5 if t he a/ d i nput si gnal i s se lected t o c ome f rom t he i nternal a nalog si gnal, t he sai ns b it f ield should be properly confgured and then the external channel input will automatically be disconnected regardless of the sacs bit feld value. after this step, go to step 6. step 6 select the reference voltgage source by confguring the savrs3~savrs0 bits. step 7 select the a/d converter output data format by confguring the adrfs bit.
rev. 1.00 1 ? 8 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 1?9 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom step 8 if a/ d c onversion i nterrupt i s u sed, t he i nterrupt c ontrol r egisters m ust b e c orrectly c onfigured to e nsure t he a/ d i nterrupt func tion i s a ctive. t he m aster i nterrupt bont rol bi t, e mi, a nd t he a/ d conversion interrupt control bit, ade, must both be set high in advance. step 9 the a/d conversion procedure can now be initialized by setting the start bit from low to high and then low again. step 10 if a/d conversion is in progress, the adbz fag will be set high. after the a/d conversion process is complete, the adbz fag will go low and then the output data can be read from sadoh and sadol registers. note: when checking for the end of the conversion process, if the method of polling the adbz bit in the sadc0 register is used, the interrupt enable step above can be omitted. programming considerations during m icrocontroller ope rations where t he a/d c onverter i s not be ing use d, t he a/d i nternal circuitry can be s witched of f to reduce pow er cons umption, by s etting bit a dcen low in the sadc0 regist er. when thi s happens, the int ernal a/ d converter ci rcuits wi ll not consume power irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the devices contain a 12-bit a/d converter , its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v ref voltage, this gives a single bit analog input value of v ref divided by 4096. 1 lsb = v ref 4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage = a/d output digital value v ref 4096 the diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he a/ d conve rter. e xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 lsb below where they would change without the of fset, and the last full scale digitised value will change at a point 1.5 lsb below the v ref level.

? ? ? ? ? ? ?? ?
? ideal a/d transfer function
rev. 1.00 1?8 ??to?e? 01? ?01? rev. 1.00 1 ? 9 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom a/d programming examples the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst example, the method of polling the adbz bit in the sadc0 register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an adbz polling method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov sadc1,a ; select f sys /8 as a/d clock and switch off vbg voltage set adcen mov a,03h ; setup acerl to confgure pin an0 mov acerl,a mov a,00h mov sadc0,a ; enable and connect an0 channel to a/d converter : start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d : polling_eoc: sz adbz ; poll the sadc0 register adbz bit to detect end of a/d conversion jmp polling_eoc ; continue polling : mov a,sadol ; read low byte conversion result value mov sadol_buffer,a ; save result to user defned register mov a,sadoh ; read high byte conversion result value mov sadoh_buffer,a ; save result to user defned register : jmp start_conversion ; start next a/d conversion
rev. 1.00 130 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 131 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom example: using the interrupt method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov sadc1,a ; select f sys /8 as a/d clock and switch off vbg voltage set adcen mov a,03h ; setup acerl to confgure pin an0 mov acerl,a mov a,00h mov sadc0,a ; enable and connect an0 channel to a/d converter : start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request fag set ade ; enable adc interrupt set emi ; enable global interrupt : : adc_isr: ; adc interrupt service routine mov acc_stack,a ; save acc to user defned memory mov a,status mov status_stack,a ; save status to user defned memory : mov a, sadol ; read low byte conversion result value mov sadol_buffer,a ; save result to user defned register mov a, sadoh ; read high byte conversion result value mov sadoh_buffer,a ; save result to user defned register : exit_int_isr: mov a,status_stack mov status,a ; restore status from user defned memory mov a,acc_stack ; restore acc from user defned memory reti
rev. 1.00 130 ??to?e? 01? ?01? rev. 1.00 131 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom serial interface module C sim these devices contain a serial interface module, which includes both the four -line spi interface or two-line i 2 c interface types, to allow an easy method of communication with external peripheral hardware. ha ving re latively si mple c ommunication prot ocols, t hese se rial i nterface t ypes a llow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash or eeprom memory , etc. the sim interface pins are pin-shared with other i/o pins and therefore the sim i nterface func tional pi ns m ust fi rst be se lected usi ng t he c orresponding pi n-shared func tion selection bits. as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using the sim operating mode control bits, named sim2~sim0, in the simc0 registe r. these pull-high resistors of the sim pin-shared i/o pins are selected using pull- high control registers when the sim function is enabled and the corresponding pins are used as sim input pins. spi interface the spi interface is often used to communicate with external peripheral devices such as sensors, flash or e eprom m emory de vices, e tc. ori ginally de veloped by mot orola, t he four l ine spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the devices can be either mas ter or s lave. a lthough the s pi interface s pecifcation can control multiple s lave devices from a single master , these devices provided only one scs pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pin to select the slave devices. spi interface operation the spi i nterface i s a f ull d uplex sy nchronous se rial d ata l ink. i t i s a f our l ine i nterface wi th p in names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines, sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin-shared with normal i/o pins and with the i 2 c function pins, the spi interface pins must frst be selected by confguring the pin-shared function selection bits and setting the correct bits in the simc0 and simc2 registers. after the desired spi confguration has been set it can be disabled or enabled us ing the s imen bit in the s imc0 regis ter. communication betw een devices connected to t he spi i nterface i s c arried out i n a sl ave/master m ode wi th a ll da ta t ransfer i nitiations be ing implemented by the master . the master also controls the clock signal. as the device only contains a single scs pin only one slave device can be utilized. the scs pin is controlled by software, set csen bit to 1 to enable scs pin function, set csen bit to 0 the scs pin will be foating state. the spi function in this device offers the following features: ? full duplex synchronous data transfer ? both master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag ? rising or falling active clock edge the status of the spi interface pins is determined by a number of facto rs such as whether the device is in the master or slave mode and upon the condition of certain control bits such as csen and simen.
rev. 1.00 13 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 133 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom spi master/slave connection

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? ? ? ? - ? ?? ? ? ?? ? ? ? spi block diagram spi registers there are three internal registers which control the overall operation of the spi interface. these are the simd data register and two registers simc0 and simc2. note that the simc1 register is only used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 simc0 sim ? sim1 sim0 simdeb1 simdeb0 simen simicf simc ? d7 d6 ckp ? lb ckeg mls csen wc ? l trf simd d7 d6 d5 d ? d3 d ? d1 d0 spi registers list simd register the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register . after the data is received from the spi bus, the device can read it from the simd register . any transmission or reception of data from the spi bus must be made via the simd register. bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r x x x x x x x x x: unknown
rev. 1.00 13? ??to?e? 01? ?01? rev. 1.00 133 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom there are also two control registers for the spi interface, simc0 and simc2. note that the simc2 register also has the name sima which is used by the i 2 c function. the simc1 register is not used by the spi functio n, only by the i 2 c function. register simc0 is used to control the enable/disable function and to set the data transmi ssion clock frequency . register simc2 is used for other control functions such as lsb/msb selection, write collision fag, etc. simc0 register bit 7 6 5 4 3 2 1 0 name sim ? sim1 sim0 simdeb1 simdeb0 simen simicf r/w r/w r/w r/w r/w r/w r/w r/w p ? r 1 1 1 0 0 0 0 bit 7~5 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is tm1 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: non sim function these bits setup the overall operatin g mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slav e selection and the spi master clock frequency . the spi clock is a function of the system clock but can also be chosen to be sourced from tm1. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 unimplemented, read as 0 bit 3~2 : i 2 c debounce t ime selection 00: no debounce 01: 2 system clock debounce 1x: 4 system clock debounce bit 1 : sim enable control 0: disable 1: enable the bi t is the overa ll on/of f control for the sim interface. when the simen bi t is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will lose their spi or i 2 c function and the sim operating current will be reduced to a mini mum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective.if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initiali sed by the applic ation program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous setti ngs and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 : sim incomplete flag 0: sim incomplete condition not occurred 1: sim incomplete condition occured this bit is only available when the sim is confgured to operate in an spi slave mode. if the spi operate s in the slave mode with the simen and csen bits both being set to 1 but the scs line is pulled high by the external master device before the spi data transfer is completely fnished, the simicf bit will be set to 1 togethe r with the trf bit. when this condition occurs, the corresponding interrupt will occur if the interrupt function is enabled. however , the trf bit will not be set to 1 if the simicf bit is set to 1 by software application program.
rev. 1.00 13 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 135 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom simc2 register bit 7 6 5 4 3 2 1 0 name d7 d6 ckp ? lb ckeg mls csen wc ? l trf r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 0 bit 7~6 undefned bits these bits can be read or written by the application program. bit 5 ckpolb : spi clock line base condition selection 0: the sck line will be high when the clock is inactive. 1: the sck line will be low when the clock is inactive. the ckpolb bi t de termines the ba se condition of the clock line, if the bi t is hi gh, then t he sck l ine wi ll be l ow whe n t he c lock i s i nactive. w hen t he ckpol b bi t i s low, then the sck line will be high when the clock is inactive. bit 4 ckeg : spi sck clock active edge type selection ckpolb=0 0: sck is high base level and data capture at sck rising edge 1: sck is high base level and data capture at sck falling edge ckpolb=1 0: sck is low base level and data capture at sck falling edge 1: sck is low base level and data capture at sck rising edge the ckeg and ckpolb bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be confgured before data transfer is e xecuted ot herwise a n e rroneous c lock e dge m ay be ge nerated. t he ckpol b bi t determines t he ba se c ondition of t he c lock l ine, i f t he bi t i s hi gh, t hen t he sck l ine will be low when the clock is inact ive. when the ckpolb bit is low , then the sck line will be high when the clock is inactive. the ckeg bit determines active clock edge type which depends upon the condition of ckpolb bit. bit 3 mls : spi data shift order 0: lsb frst 1: msb frst this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 csen : spi scs pin control 0: disable 1: enable the csen bit is used as an enable/disable for the scs pin. if this bit is low , then the scs pin will be disabled and placed into i/o pin or other pin-shared functions. if the bit is high, the scs pin will be enabled and used as a select pin. bit 1 wcol : spi write collision fag 0: no collision 1: collision the wcol fag is used to detect whether a data collision has occurred or not. if this bit is high, it means that data has been attempted to be written to the simd register duting a data transfer operation. this writing operation will be ignored if data is being transferred. this bit can be cleared by the application program. bit 0 trf : spi t ransmit/receive complete fag 0: spi data is being transferred 1: spi data transfer is completed the trf bit is the t ransmit/receive complete fag and is set to 1 automatically when an spi data transfer is completed, but must cleared to 0 by the application program. it can be used to generate an interrupt.
rev. 1.00 13? ??to?e? 01? ?01? rev. 1.00 135 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom spi communication after t he spi i nterface i s e nabled by se tting t he sime n bi t hi gh, t hen i n t he ma ster mode , whe n data is written to the simd register , transmission/reception will begin simultaneously . when the data t ransfer i s c omplete, t he t rf fl ag wi ll be se t a utomatically, but m ust be c leared usi ng t he application program. in the slave mode, when the clock signal from the master has been received, any data in the simd register will be transmitted and any data on the sdi pin will be shifted into the simd register . the master should output a scs signal to enable the slave devices before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scs signal depending upon the confgurations of the ckpolb bit and ckeg bit. the accompanying timing diagram shows the relationship between the slave data and scs signal for various confgurations of the ckpolb and ckeg bits. the spi master mode will continue to function even in the idle1 mode if the selected spi clock source is running.
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?? ?? ? ?? ? ?? ?? -? ?? ?? ?? ?? ?? -? ?? ? ?? ?? ? ?? ?? ?? ? ?? ? ?? ?? -? ?? ?? ?? ?? ?? -? ?? ? ?? ?? ? ?? ?
? ? spi master mode timing

? ? ? ? ??? ? - ? ? ?? spi slave mode timing C ckeg = 0
rev. 1.00 136 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 137 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom

? ? ??? ?? ? ? ? ?? ?? ? - ? ?? ?? ? ? ?? ? ? ? ? ?? ? ?? ?? ?? ? ? ? ? ?? ? ?? ? ?? ? ?? ? ? ?? ? note: for spi slave mode, if simen=1 and csen=0, the spi is always enabled and ignores the scs level. spi slave mode timing C ckeg = 1

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? ? ? ? ? ? -? ?? ? ? ? ? ? ? ???? ??? ? ????? ?? ?? ? ???? ? spi transfer control flow chart
rev. 1.00 136 ??to?e? 01? ?01? rev. 1.00 137 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom m emory e tc. or iginally d eveloped b y ph ilips, i t i s a t wo l ine l ow sp eed se rial i nterface for synchronous serial data transfer . the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c master slave bus connection i 2 c interface operation the i 2 c serial interface is a two line interf ace, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two device s communicate with each other on the bidirectional i 2 c bus, one is known as the master de vice a nd one a s t he sl ave de vice. bot h m aster a nd sl ave c an t ransmit a nd re ceive da ta, however, it is the master device that has overall control of the bus. for these devices, which only operate in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode.

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? ?? ? i 2 c block diagram
rev. 1.00 138 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 139 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom
the simdeb1 and simdeb0 bits determine the debounce time of the i 2 c interface. this uses the system clock to in ef fect add a debounce time to the external clock to reduce the possibility of gl itches on t he c lock l ine c ausing e rroneous ope ration. t he de bounce t ime, i f se lected, c an be chosen to be either 2 or 4 sys tem clocks. t o achieve the required i 2 c data trans fer speed, there exists a relationship between the system clock, f sys , and the i 2 c debounce time. for either the i 2 c standard or fast mode operation, users must take care of the selected system clock frequency and the confgured debounce time to match the criterion shown in the following table. i 2 c debounce time selection i 2 c standard mode (100khz) i 2 c fast mode (400khz) no devoun ? e f sys > ? mhz f sys > 5 mhz ? system ? lo ? k de ? oun ? e f sys > ? mhz f sys > 10 mhz ? system ? lo ? k de ? oun ? e f sys > 8 mhz f sys > ? 0 mhz i 2 c minimum f sys frequency i 2 c registers there a re t hree c ontrol re gisters a ssociated wi th t he i 2 c bus, simc0, simc1 a nd simt oc, one slave address register , sima, and one data register , simd. the simd register , which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. before the micro controller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register . after the data is received from the i 2 c bus, the microcontroller can read it from the simd register . any transmission or reception of data from the i 2 c bus must be made via the simd register. note that the sima register also has the name simc2 which is used by the spi function. bit simen and bits sim2~sim0 in register simc0 are used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 simc0 sim ? sim1 sim0 simdeb1 simdeb0 simen simicf simc1 hcf haas hbb htx txak srw iamwu rxak sima iica6 iica5 iica ? iica3 iica ? iica1 iica0 d0 simd d7 d6 d5 d ? d3 d ? d1 d0 simt ? c simt ? en simt ? f simt ? s5 simt ? s ? simt ? s3 simt ? s ? simt ? s1 simt ? s0 i 2 c registers list
rev. 1.00 138 ??to?e? 01? ?01? rev. 1.00 139 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom simd register the simd register is used to store the data being transmitted and received. the same register is used by bot h t he spi a nd i 2 c fun ctions. be fore t he de vice wri tes da ta t o t he i 2 c bus, t he a ctual da ta t o be transmitted must be placed in the simd register . after the data is received from the i 2 c bus, the device can read it from the simd register . any transmission or reception of data from the i 2 c bus must be made via the simd register. bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r x x x x x x x x x: unknown sima register the sima registe r is also used by the spi interface but has the name simc2. the sima register is the location where the 7-bit slave address of the slave device is stored. bits 7~1 of the sima register defne the device slave address. bit 0 is not defned. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the sima register , the slave device will be selected. note that the sima register is the same register address as simc2 which is used by the spi interface. bit 7 6 5 4 3 2 1 0 name iica6 iica5 iica ? iica3 iica ? iica1 iica0 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r x x x x x x x x x: unknown bit 7~1 : i 2 c slave address iica6~iica0 is the i 2 c slave address bit 6 ~ bit 0 bit 0 undefned bit the bit can be read or written by the application program. there are also three control registers for the i 2 c interface, simc0, simc1 and simt oc. the register simc0 is used to control the enable/disable function and to set the data transmission clock fre quency.the simc1 re gister c ontains t he rel evant fa gs whi ch a re use d t o i ndicate t he i 2 c communication status. the simt oc register is used to control the i 2 c bus time-out function which is described in the i 2 c t ime-out control section.
rev. 1.00 1 ? 0 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 1?1 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom simc0 register bit 7 6 5 4 3 2 1 0 name sim ? sim1 sim0 simdeb1 simdeb0 simen simicf r/w r/w r/w r/w r/w r/w r/w r/w p ? r 1 1 1 0 0 0 0 bit 7~5 sim2~sim0 : sim operating mode control 000: spi master mode; spi clock is f /4 001: spi master mode; spi clock is f /16 010: spi master mode; spi clock is f /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is tm1 ccrp match frequency/2 101: spi slave mode 110: i c slave mode 111: non sim function these bits setup the overall operatin g mode of the sim function. as well as selecting if the i c or spi function, they are used to control the spi master/slav e selection and the spi master clock frequency . the spi clock is a function of the system clock but can also be chosen to be sourced from tm1. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 unimplemented, read as 0 bit 3~2 simdeb1~simdeb0 : i c debounce t ime selection 00: no debounce 01: 2 system clock debounce 1x: 4 system clock debounce bit 1 simen : sim enable control 0: disable 1: enable the bi t is the overa ll on/of f control for the sim interface. when the simen bi t is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will lose their spi or i c function and the sim operating current will be reduced to a mini mum value. when the bit is high the sim interface is enabled. the sim confguration option must have frst enabled the sim interface for this bit to be effective.if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initiali sed by the applic ation program. if the sim is confgured to operate as an i c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i c control bits such as htx and txak will remain at the previous setti ngs and should therefore be first initialised by the application program while the relevant i c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 simicf : sim incomplete flag 0: sim incomplete condition not occurred 1: sim incomplete condition occured this bit is only available when the sim is confgured to operate in an spi slave mode. if the spi operate s in the slave mode with the simen and csen bits both being set to 1 but the scs line is pulled high by the external master device before the spi data transfer is completely fnished, the simicf bit will be set to 1 togethe r with the trf bit. when this condition occurs, the corresponding interrupt will occur if the interrupt function is enabled. however , the trf bit will not be set to 1 if the simicf bit is set to 1 by software application program.
rev. 1.00 1?0 ??to?e? 01? ?01? rev. 1.00 1 ? 1 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom simc1 register bit 7 6 5 4 3 2 1 0 name hcf haas hbb htx txak srw iamwu rxak r/w r r r r/w r/w r/w r/w r p ? r 1 0 0 0 0 0 0 1 bit 7 hcf : i c bus data transfer completion fag 0: data is being transferred 1: completion of an 8-bit data transfer the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. bit 6 haas : i c bus data transfer completion fag 0: not address match 1: address match the haas fa g i s t he a ddress m atch fa g. t his fa g i s use d t o de termine i f t he sl ave device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the fag will be low. bit 5 hbb : i c bus busy fag 0: i c bus is not busy 1: i c bus is busy the hbb flag is the i c busy flag. this flag will be 1 when the i c bus is busy which will occur when a st art signal is detected. the fag will be set to 0 when the bus is free which will occur when a stop signal is detected. bit 4 htx : i c slave device transmitter/receiver selection 0: slave device is the receiver 1: slave device is the transmitter bit 3 txak : i c bus transmit acknowledge fag 0: slave send acknowledge fag 1: slave does not send acknowledge fag the txak bit is the transmit acknowledge fag. after the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9 th clock from the slave device. the slave device must always set txak bit to 0 before further data is received. bit 2 srw : i c slave read/write fag 0: slave device should be in receive mode 1: slave device should be in transmit mode the sr w f lag i s t he i c sl ave r ead/write f lag. t his f lag d etermines wh ether the master device wishes to transmit or receive data from the i c bus. when the transmitted address and slave address is match, that is when the haas fag is set high, the slave device will check the sr w fag to determine whether it should be in transmit mode or receive mode. if the sr w fag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. when the sr w flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 iamwu : i c address match w ake-up control 0: disable 1: enable C must be cleared by the application program after wake-up this bit should be set to 1 to enabl e the i c address match wake up from the sleep or idle mode. if the iamwu bit has been set before entering either the sleep or idle mode to enable the i c address match wake up, then this bit must be cleared by the application program after wake-up to ensure correction device operation.
rev. 1.00 1 ?? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 1?3 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom bit 0 rxak : i 2 c bus receive acknowledge fag 0: slave receives acknowledge fag 1: slave does not receive acknowledge fag the r xak fl ag i s t he r eceiver a cknowledge f lag. w hen t he r xak f lag i s 0, i t means that a acknowledge signal has been received at the 9 th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks the rxak fag to determine if the master receiver wishes to receive the next byte. t he sl ave t ransmitter wi ll t herefore c ontinue se nding out da ta unt il t he rxak fag is 1. when this occurs, the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. communication on the i 2 c bus requires four separate steps, a st art signal, a slave device address transmission, a data transmission and finally a st op signal. when a st art signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must frst check the condition of the haas and simt of bits to determine whether t he i nterrupt sou rce o riginates fr om a n a ddress m atch, 8 -bit d ata t ransfer c ompletion o r i 2 c bus time-out occurrence. during a data transfer , note that after the 7-bit slave address has been transmitted, the following bit, which is the 8 th bit, is the read/write bit whose value will be placed in the srw bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must initialise the bus, the following are steps to achieve this: ? step 1 set the sim2~sim 0 bits to 1 10 and simen bit to 1 in the simc0 register to enable the i 2 c bus. ? step 2 write the slave address of the device to the i 2 c bus address register sima. ? step 3 set the sime interrupt enable bit of the interrupt control register to enable the sim interrupt.

? ? ? ? ?? ? - ? ?? ? ? ? ? ?? i 2 c bus initialisation flow chart
rev. 1.00 1?? ??to?e? 01? ?01? rev. 1.00 1 ? 3 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom i 2 c bus start signal the st art signal can only be generated by the master device connec ted to the i 2 c bus and not by the slave device. this st art signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a st art condition occurs when a high to low transition on the sda line takes place when the scl line remains high. i 2 c slave address the t ransmission o f a st art si gnal b y t he m aster wi ll b e d etected b y a ll d evices o n t he i 2 c b us. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the st art signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the maste r matche s the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal will be generated. the next bit following the address, which is the 8 th bit, defnes the read/write status and will be saved to the sr w bit of the simc1 register . the slave device will then transmit an acknowledge bit, which is a low level, as the 9 th bit. the slave device will also set the status fag haas when the addresses match. as a n i 2 c bus i nterrupt c an c ome fro m t hree sourc es, whe n t he progra m e nters t he i nterrupt subroutine, the haas and simt of bits should be examined to see whether the interrupt source has come from a matching slave address, the completion of a data byte transfer or the i 2 c bus time-out occurrence. when a slave address is matched, the devices must be placed in either the transmit mode and then write data to the simd register , or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c bus read/write signal the sr w bit in the simc1 registe r defnes whether the slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver . if the sr w fag is 1 then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter . if the sr w fag is 0 then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver. i 2 c bus slave address acknowledge signal after the mas ter has trans mitted a calling addres s, any s lave device on the i 2 c bus , w hose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a st op signal must be transmitted by the master to end the communication. when the haas fag is high, the addresses have matched and the slave device must check the sr w fag to determine if it is to be a transmitter or a receiver . if the sr w fag is high, the slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set to 1. if the sr w fag is low , then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be set to 0.
rev. 1.00 1 ?? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 1?5 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom i 2 c bus data and acknowledge signal the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt o f i ts sl ave a ddress. t he o rder o f se rial b it t ransmission i s t he msb fr st a nd t he l sb l ast. after receipt of 8-bits of data, the receiver must transmit an acknowle dge signal, level 0, before it can receive the next data byte. if the slave transmitter does not recei ve an acknowledge bit signal from the master receiver , then the slave transmitter will release the sda line to allow the master to send a st op signal to release the i 2 c bus. the corresponding data will be stored in the simd register. if setup as a transmitter , the slave device must frst write the data to be transmitted into the simd register . if setup as a receive r, the slave device must read the transmitted data from the simd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as txak, on the 9 th clock. the slave device, which is setup as a transmi tter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master.
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- ? ? note: * when a slave address is matched, the devices mus t be placed in either the trans mit mode and then write data to the simd register , or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c communication timing diagram
rev. 1.00 1?? ??to?e? 01? ?01? rev. 1.00 1 ? 5 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom
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?? ? ?? i 2 c bus isr flow chart i 2 c time-out control in order to reduce the i 2 c lockup problem due to reception of erroneous clock sources , a time-out function is provided. if the clock source connected to the i 2 c bus is not received for a while, then the i 2 c circu itry and registers will be reset after a certain time-out period. the time-out counter starts to count on an i 2 c bus st art & address match condition, and is cle ared by an scl falling edge. before the next s cl falling edge arrives , if the time elaps ed is greater than the time-out period specifed by the simt oc register , then a time-out condition will occur . the time-out function will stop when an i 2 c stop condition occurs.
rev. 1.00 1 ? 6 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 1?7 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom

i 2 c time-out when an i 2 c time-out counter overfow occurs, the counter will stop and the simt oen bit will be c leared t o z ero a nd t he simt of bi t wi ll be se t hi gh t o i ndicate t hat a t ime-out c ondition ha s occurred. the time-out condition will also generate an interrupt which uses the i 2 c interrrupt vector . when an i 2 c time-out occurs, the i 2 c internal circuitry will be reset and the registers will be reset into the following condition: register after i 2 c time-out simd ? sima ? simc0 no ? hange simc1 reset to p ? r ? ondition i 2 c register after time-out the simtof fag can be cleared by the application program. there are 64 time-out period selections which can be selected using the simt os bits in the simt oc register . the time-out duration is calculated by the formula: ((1~64) (32/f sub )). this gives a time-out period which ranges from about 1ms to 64ms. simtoc register bit 7 6 5 4 3 2 1 0 name simt ? en simt ? f simt ? s5 simt ? s ? simt ? s3 simt ? s ? simt ? s1 simt ? s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 0 bit 7 : sim i 2 c t ime-out function control 0: disable 1: enable bit 6 : sim i 2 c t ime-out fag 0: no time-out occurred 1: t ime-out occurred bit 5~0 : sim i 2 c t ime-out period selection i 2 c t ime-out clock source is f sub /32 i 2 c t ime-out period is equal to (i2ctos[5:0] + 1) 32 f sub
rev. 1.00 1?6 ??to?e? 01? ?01? rev. 1.00 1 ? 7 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom comparators an analog comparator is contained only within the ht66f0185 device. the comparator function offers fexibility via their register controlled features such as power -down, polarity select, hysteresis etc. in sharing their pins with normal i/o pins the comparators do not waste precious i/o pins if there functions are otherwise unused.

comparator comparator operation the ht66f0185 device contains a comparator function which is used to compare two analog voltages and provide an output based on their dif ference. full control over the internal comparator is provided via the control register cpc assigned to the comparator . the comparator output is recorded via a bit in the control register , but can also be transferred out onto a shared i/o pin. additional comparator functions include output polarity, hysteresis functions and power down control. any pull-high resistors connected to the shared comparator input pins will be automatically disconnected when the comparator is enabled. as the comparator inputs approach their switching level, so me sp urious o utput si gnals m ay b e g enerated o n t he c omparator o utput d ue t o t he sl ow rising or falling nature of the input signals. this can be minimised by selecting the hysteresis function wh ich a pplies a sm all a mount o f p ositive f eedback t o t he c omparator. i deally t he comparator should switch at the point where the positive and negative inputs signals are at the same voltage level. however , unavoidable input of fsets introduce some uncertainties here. the hysteresis function, if enabled, also increases the switching offset value. comparator interrupt the comparator possesses its own interrupt function. when the comparator output changes state, its releva nt interru pt fag will be set, and if the corresponding interrupt enable bit is set, then a jump to its rele vant inte rrupt vector will be executed. note that it is the changing state of the cout bit and not the output pin which generates an interrupt. if the microcontroller is in the sleep or idle mode and the comparator is enabled, then if the external input lines cause the comparator output to change state, the resulting generate d interrupt fag will also generate a wake-up. if it is required to disable a wake-up from occurring, then the interrupt fag should be frst set high before entering the sleep or idle mode. programming considerations if the comparator is enabled, it will remain active when the microcontroller enters the sleep or idle mode, however as it will consume a certain amount of power , the user may wish to consider disabling it before the sleep or idle mode is entered. as comparator pins are shared with normal i/o pins, the i/o registers for these pins will be read as zero (port control register is 1) or read as port data register value (port control register is 0) if the comparator function is enabled.
rev. 1.00 1 ? 8 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 1?9 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom cpc register bit 7 6 5 4 3 2 1 0 name csel cen cp ? l c ? ut c ? s cmpeg1 cmpeg0 chyen r/w r/w r/w r/w r r/w r/w r/w r/w p ? r 1 0 0 0 0 0 0 1 bit 7 csel : select comparator pins or i/o pins 0: i/o pin selected 1: comparator input pins c+ and c- selected this is the comparator input pin or i/o pin select bit. if the bit is high the comparator input pins will be enabled. as a result, these two pins will lose their i/o pin functions. any pull-high confguration options associated with the comparator shared pins will also be automatically disconnected. bit 6 cen : comparator on/off control 0: off 1: on this i s t he com parator on/ off c ontrol bi t. if t he bi t i s z ero t he c omparator wi ll be switched of f and no power consumed even if analog voltages are applied to its inputs. for power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the sleep or idle mode. bit 5 cpol : comparator output polarity 0: output not inverted 1: output inverted this is the comparator polarity bit. if the bit is zero then the cout bit will refect the non-inverted output condition of the comparator . if the bit is high the comparator cout bit will be inverted. bit 4 cout : comparator output bit cpol = 0 0: c+ < c1 1: c+ > c- cpol = 1 0: c+ > c1 1: c+ < c- this bit stores the comparator output bit. the polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the cpol bit. bit 3 cos : comparator output path select 0: cx pin selected (compare output can output to cx pin) 1: i/o pin selected (compare output only internal use) bit 2~1 cmpeg1~cmpeg0 : comparator output interrupt trigger edge select 00: rising edge comparator interrupt trigger signal generated if cout changed state from 0 to 1 01: falling edge comparator interrupt trigger signal generated if cout changed state from 1 to 0 1x: both edge comparator interrupt trigger signal generated if cout changed state from 0 to 1 or 1 to 0 bit 0 chyen : comparator hysteresis function control 0: off 1: on this is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator , as specifed in the comparator electrical characteristics table. the positive feedback induced by hysteresis reduces the ef fect of spurious switching near the comparator threshold.
rev. 1.00 1?8 ??to?e? 01? ?01? rev. 1.00 1 ? 9 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom scom/sseg function for lcd the devices have the capability of driving external lcd panels. the common and segment pins for lcd driving, scom0~scom5 and sseg0~sseg19 or sseg0~sseg23, are pin-shared with certain pins on the i/o ports. the lcd signals, com and seg, are generated using the application program. lcd operation an external lcd panel can be driven using the devices by confguring the i/o pins as common pins and and segment pins. the lcd driver function is controlled using the lcd control registers which in addition to controlling the overall on/of f function also controls the r-type bias current on the scom and sseg pins. this enables the lcd com and seg driver to generate the necessary v ss , (1/3)v dd , (2/3)v dd and v dd voltage levels for lcd 1/3 bias operation. the lcden bit in the slcdc0 register is the overall master control for the lcd driver . this bit is used in conjunction with the comnen and segnen bits to select which i/o pins are used for lcd driving. not e t hat t he c orresponding port cont rol regi ster doe s not ne ed t o frst se tup t he pi ns a s outputs to enable the lcd driver operation. v dd (?/3) v dd (1/3) v dd v dd lcd voltage select circuit lcd com/seg analog switch lcden isel[1:0] c?mnen c?msegsn 66 segmen frame sc?m0/sseg0 sc?m5/sseg5 sseg6 ssegm m = 19 fo? HT66F0175 m = ?3 fo? ht66f0185 software controlled lcd driver structure
rev. 1.00 150 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 151 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom lcd frames a c yclic l cd wa veform i ncludes t wo f rames k nown a s fr ame 0 a nd fr ame 1 f or wh ich t he following offers a functional explanation. ? frame 0 to select frame 0, clear the frame bit in the slcdc 0 register to 0. in frame 0, the com signal output can have a value of v dd or a v bias value of (1/3)v dd . the seg signal output can have a value of v ss or a v bias value of (2/3)v dd . ? frame 1 to select frame 1, set the frame bit in the slcdc0 register to 1. in frame 1, the com signal output can have a value of v ss or a v bias value of (2/3)v dd . the seg signal output can have a value of v dd or a v bias value of (1/3)v dd . the comn wa veform i s c ontrolled by t he a pplication program usi ng t he frame bi t i n t he slcdc0 register and the corresponding pin-shared i/o data bit for the respective com pin to determine whe ther t he comn out put ha s a va lue of v dd , v ss or v bias . t he se gm wa veform i s controlled in a similar way using the frame bit and the corresponding pin-shared i/o data bit for the respective seg pin to determine whether the segm output has a value of v dd , v ss or v bias . the accompanying w aveform diagram s hows a typical 1/3 bias lcd w aveform gemerated us ing the application program together with the lcd voltage select circuit. note that the depiction of a 1 in the diagram illustrates an illu minated lcd pixel. the com signal polarity generated on pins scom0~scom5, wh ether 0 or 1, a re ge nerated usi ng t he c orresponding pi n-shared i/ o da ta register bit. com0 v dd (2/3) v dd (1/3) v dd v ss v dd (2/3) v dd (1/3) v dd v ss com1 com2 v dd (2/3) v dd (1/3) v dd v ss v dd (2/3) v dd (1/3) v dd v ss com3 v dd (2/3) v dd (1/3) v dd v ss seg0 v dd (2/3) v dd (1/3) v dd v ss seg1 frame 0 frame 1 frame 0 frame 1 frame 0 frame 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 note: the logical values shown in the above diagram are the corresponding pin-shared i/o data bit value. 1/3 bias lcd waveform C 4-com & 2-seg application
rev. 1.00 150 ??to?e? 01? ?01? rev. 1.00 151 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom lcd control registers the lcd com and seg driver enables a range of selections to be provided to suit the requirement of the lcd panel which is being used. the bias resistor choice is implemented using the isel1 and ise l0 bi ts i n t he sl cdc0 re gister. al l com a nd se g pi ns a re pi n-shared wi th i/ o pi ns a nd selected as com and seg pins using the corresponding pin function selection bits in the slcdcn registers respectively. register name bit 7 6 5 4 3 2 1 0 slcdc0 frame isel1 isel0 lcden c ? m3en c ? m ? en c ? m1en c ? m0en slcdc1 c ? m5en c ? m ? en c ? msegs5 c ? msegs ? c ? msegs3 c ? msegs ? c ? msegs1 c ? msegs0 slcdc ? seg13en seg1 ? en seg11en seg10en seg9en seg8en seg7en seg6en slcdc3 seg19en seg18en seg17en seg16en seg15en seg1 ? en lcd driver control registers list C HT66F0175 register name bit 7 6 5 4 3 2 1 0 slcdc0 frame isel1 isel0 lcden c ? m3en c ? m ? en c ? m1en c ? m0en slcdc1 c ? m5en c ? m ? en c ? msegs5 c ? msegs ? c ? msegs3 c ? msegs ? c ? msegs1 c ? msegs0 slcdc ? seg13en seg1 ? en seg11en seg10en seg9en seg8en seg7en seg6en slcdc3 seg ? 1en seg ? 0en seg19en seg18en seg17en seg16en seg15en seg1 ? en slcdc ? seg ? 3en seg ?? en lcd driver control registers list C ht66f0185 slcdc0 register bit 7 6 5 4 3 2 1 0 name frame isel1 isel0 lcden c ? m3en c ? m ? en c ? m1en c ? m0en r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 0 bit 7 frame : scom/sseg output frame selection 0: frame 0 1: frame 1 bit 6~5 isel1~isel0 : select scom/sseg typical bias current (v =5v) 00: 8.3a 01: 16.7a 10: 50a 11: 100a bit 4 lcden : scom/sseg module enable control 0: disable 1: enable the scomn and ssegm lines can be enabled using comnen and segmen if the lcden bit is set to 1. when the lcd bit is cleared to 0, then the scomn and ssegm outputs will be fxed at a v level. bit 3 com3en : scom3/sseg3 or other pin function select 0: other pin-shared functions 1: scom3/sseg3 function bit 2 com2en : scom2/sseg2 or other pin function select 0: other pin-shared functions 1: scom2/sseg2 function
rev. 1.00 15 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 153 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom bit 1 com1en : scom1/sseg1 or other pin function select 0: other pin-shared functions 1: scom1/sseg1 function bit 0 com0en : scom0/sseg0 or other pin function select 0: other pin-shared functions 1: scom0/sseg0 function slcdc1 register bit 7 6 5 4 3 2 1 0 name c ? m5en c ? m ? en c ? msegs5 c ? msegs ? c ? msegs3 c ? msegs ? c ? msegs1 c ? msegs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 0 bit 7 com5en : scom5/sseg5 or other pin function select 0: other pin-shared functions 1: scom5/sseg5 function bit 6 com4en : scom4/sseg4 or other pin function select 0: other pin-shared functions 1: scom4/sseg4 function bit 5 comsegs5 : scom5 or sseg5 pin function select 0: scom5 1: sseg5 bit 4 comsegs4 : scom4 or sseg4 pin function select 0: scom4 1: sseg4 bit 3 comsegs3 : scom3 or sseg3 pin function select 0: scom3 1: sseg3 bit 2 comsegs2 : scom2 or sseg2 pin function select 0: scom2 1: sseg2 bit 1 comsegs1 : scom1 or sseg1 pin function select 0: scom1 1: sseg1 bit 0 comsegs0 : scom0 or sseg0 pin function select 0: scom0 1: sseg0
rev. 1.00 15? ??to?e? 01? ?01? rev. 1.00 153 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom slcdc2 register bit 7 6 5 4 3 2 1 0 name seg13en seg1 ? en seg11en seg10en seg9en seg8en seg7en seg6en r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 0 bit 7 seg13en : sseg13 pin function select 0: other pin-shared functions 1: sseg13 function bit 6 seg12en : sseg12 pin function select 0: other pin-shared functions 1: sseg12 function bit 5 seg11en : sseg11 pin function select 0: other pin-shared functions 1: sseg11 function bit 4 seg10en : sseg10 pin function select 0: other pin-shared functions 1: sseg10 function bit 3 seg9en : sseg9 pin function select 0: other pin-shared functions 1: sseg9 function bit 2 seg8en : sseg8 pin function select 0: other pin-shared functions 1: sseg8 function bit 1 seg7en : sseg7 pin function select 0: other pin-shared functions 1: sseg7 function bit 0 seg6en : sseg6 pin function select 0: other pin-shared functions 1: sseg6 function
rev. 1.00 15 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 155 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom slcdc3 register C HT66F0175 bit 7 6 5 4 3 2 1 0 name seg19en seg18en seg17en seg16en seg15en seg1 ? en r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 seg19en : sseg19 pin function select 0: other pin-shared functions 1: sseg19 function bit 4 seg18en : sseg18 pin function select 0: other pin-shared functions 1: sseg18 function bit 3 seg17en : sseg17 pin function select 0: other pin-shared functions 1: sseg17 function bit 2 seg16en : sseg16 pin function select 0: other pin-shared functions 1: sseg16 function bit 1 seg15en : sseg15 pin function select 0: other pin-shared functions 1: sseg15 function bit 0 seg14en : sseg14 pin function select 0: other pin-shared functions 1: sseg14 function
rev. 1.00 15? ??to?e? 01? ?01? rev. 1.00 155 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom slcdc3 register C ht66f0185 bit 7 6 5 4 3 2 1 0 name seg ? 1en seg ? 0en seg19en seg18en seg17en seg16en seg15en seg1 ? en r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 0 bit 7 seg21en : sseg21 pin function select 0: other pin-shared functions 1: sseg21 function bit 6 seg20en : sseg20 pin function select 0: other pin-shared functions 1: sseg20 function bit 5 seg19en : sseg19 pin function select 0: other pin-shared functions 1: sseg19 function bit 4 seg18en : sseg18 pin function select 0: other pin-shared functions 1: sseg18 function bit 3 seg17en : sseg17 pin function select 0: other pin-shared functions 1: sseg17 function bit 2 seg16en : sseg16 pin function select 0: other pin-shared functions 1: sseg16 function bit 1 seg15en : sseg15 pin function select 0: other pin-shared functions 1: sseg15 function bit 0 seg14en : sseg14 pin function select 0: other pin-shared functions 1: sseg14 function slcdc4 register C ht66f0185 bit 7 6 5 4 3 2 1 0 name seg ? 3en seg ?? en r/w r/w r/w p ? r 0 0 bit 7~2 unimplemented, read as 0 bit 1 seg23en : sseg23 pin function select 0: other pin-shared functions 1: sseg23 function bit 0 seg22en : sseg22 pin function select 0: other pin-shared functions 1: sseg22 function
rev. 1.00 156 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 157 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom uart interface the uar t i nterface m odule i s only cont ained i n t he ht 66f0185 devi ce. t he ht 66f0185 devi ce contains an integrated full-duplex asynchronous serial communications uar t interface that enables communication with external devic es that contain a serial interface. the uar t function has many features a nd c an t ransmit a nd r eceive d ata se rially b y t ransferring a f rame o f d ata wi th e ight o r nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. the ua rt function poss esses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. the integrated uart function contains the following features: ? full-duplex, asynchronous communication ? 8 or 9 bits character length ? even, odd or no parity options ? one or two stop bits ? baud rate generator with 8-bit prescaler ? parity, framing, noise and overrun error detection ? support for interrupt on address detect (last character bit=1) ? separately enabled transmitter and receiver ? 2-byte deep fifo receive data buffer ? t ransmit and receive interrupts ? interrupts can be initialized by the following conditions: ? transmitter empty ? transmitter idle ? receiver full ? receiver overrun ? address mode detect msb lsb t?ansmitte? shift registe? (tsr) msb lsb re?eive? shift registe? (rsr) tx pin rx pin baud rate gene?ato? tx registe? (txr) rx registe? (rxr) data to ?e t?ansmitted data ?e?eived buffe? f sys mcu data bus uart data transfer block diagram
rev. 1.00 156 ??to?e? 01? ?01? rev. 1.00 157 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom uart external pin to communicate with an external serial interface, the internal uar t has two external pins known as tx and rx. the tx and rx pins are respectively the uar t transmitter and receiver pins which are pin-shared with i/o or other pin-shared functions. along with the uar ten bit, the txen and rxen bits, if set, will automatically setup these i/o pins to their respective tx output and rx input conditions and disable any pull-high resistor option which may exist on the tx and rx pins. when the tx or rx pin function is disabled by clearing the uar ten, txen or rxen bit, the tx or rx pin w ill be us ed as i/o or other pin-s hared functional pin depending upon the pin-s hared function priority. uart data transfer scheme the a bove di agram shows t he ove rall da ta t ransfer st ructure a rrangement for t he uar t i nterface. the a ctual da ta t o be t ransmitted from t he mcu i s fi rst t ransferred t o t he t xr re gister by t he application program. the data will then be transferred to the t ransmit shift register from where it will be shifted out, lsb frst, onto the tx pin at a rate controlled by the baud rate generator . only the txr register is mapped onto the mcu data memory , the transmit shift register is not mapped and is therefore inaccessible to the application program. data to be received by the uar t is accepted on the external rx pin, from where it is shifted in, lsb fi rst, t o t he re ceiver shi ft r egister a t a ra te c ontrolled by t he b aud ra te ge nerator. w hen the shift register is full, the data will then be transferred from the shift register to the internal rxr register, where it is buf fered and can be manipulated by the application program. only the txr register i s m apped ont o t he mcu da ta me mory, t he re ceiver shift re gister i s not m apped a nd i s therefore inaccessible to the application program. it should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate txr and rxr registers, only exists as a single shared register in the data memory . this shared register known as the txr_rxr register is used for both data transmission and data reception. uart status and control registers there are fve control registers associated with the uar t function. the usr, ucr1 and ucr2 registers c ontrol t he o verall f unction o f t he uar t, wh ile t he b rg r egister c ontrols t he b aud r ate. the actua l data to be transmitted and received on the serial interface is managed through the txr_ rxr data registers. register name bit 7 6 5 4 3 2 1 0 usr perr nf ferr ? err ridle rxif tidle txif ucr1 uarten bn ? pren prt st ? ps txbrk rx8 tx8 ucr ? txen rxen brgh adden wake rie tiie teie brg brg7 brg6 brg5 brg ? brg3 brg ? brg1 brg0 txr_rxr txrx7 txrx6 txrx5 txrx ? txrx3 txrx ? txrx1 txrx0 uart status and control registers list C ht66f0185 only
rev. 1.00 158 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 159 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom txr_rxr register the txr_rxr register is the data register which is used to store the data to be transmitted on the tx pin or being received from the rx pin. bit 7 6 5 4 3 2 1 0 name txrx7 txrx6 txrx5 txrx ? txrx3 txrx ? txrx1 txrx0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r x x x x x x x x x: unknown bit 7~0 txrx7~txrx0 : uart t ransmit/receive data bits usr register the usr r egister i s t he st atus r egister f or t he uar t, wh ich c an b e r ead b y t he p rogram t o determine the present status of the uar t. all fags within the usr register are read only and further explanations are given below. bit 7 6 5 4 3 2 1 0 name perr nf ferr ? err ridle rxif tidle txif r/w r r r r r r r r p ? r 0 0 0 0 1 0 1 1 bit 7 perr : parity error fag 0: no parity error is detected 1: parity error is detected the perr fag is the parity error fag. when this read only fag is 0, it indicates a parity error has not been detected. when the fag is 1, it indicates that the parity of the received word is incorrect. this error fag is applicable only if parity mode (odd or even) is selected. the fag can also be cleared by a software sequence which involves a read to the status register usr followed by an access to the rxr data register. bit 6 nf : noise fag 0: no noise is detected 1: noise is detected the nf fag is the noise fag. when this read only fag is 0, it indicates no noise condition. when the fag is 1, it indicates that the uar t has detected noise on the receiver input. the nf fag is set during the same cycle as the rxif fag but will not be set in the case of as overrun. the n f fag can be cleared by a softw are sequence which will involve a read to the status register usr followed by an access to the rxr data register. bit 5 ferr : framing error fag 0: no framing error is detected 1: framing error is detected the ferr fag is the framing error fag. when this read only fag is 0, it indicates that t here i s n o f raming e rror. w hen t he fa g i s 1, i t i ndicates t hat a f raming e rror has been detected for the current character . the fag can also be cleared by a software sequence which will involve a read to the status register usr followed by an access to the rxr data register.
rev. 1.00 158 ??to?e? 01? ?01? rev. 1.00 159 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom bit 4 oerr : overrun error fag 0: no overrun error is detected 1: overrun error is detected the oerr fag is the overrun error fag which indicates when the rece iver buf fer has overfowed. when this read only fag is 0, it indicates that there is no overrun error . when the fag is 1, it indicates that an overrun error occurs which will inhibit further transfers to the rxr receive data register . the fag is cleared by a software sequence, which is a read to the s tatus regis ter u sr follow ed by an acces s to the rx r data register. bit 3 ridle : receiver status 0: data reception is in progress (data being received) 1: no data reception is in progress (receiver is idle) the ridle fag is the receiver status fag. when this read only fag is 0, it indicates that the receiver is between the init ial detection of the start bit and the completion of the s top bit. when the f ag is 1, it indicates that the receiver is idle. betw een the completion of the stop bit and the detection of the next start bit, the ridle bit is 1 indicating that the uart receiver is idle and the rx pin stays in logic high condition. bit 2 rxif : receive rxr data register status 0: rxr data register is empty 1: rxr data register has available data the rxif fag is the receive data register status fag. when this read only fag is 0, it indicates that the rxr read data register is empty . when the fag is 1, it indicates that t he r xr r ead d ata r egister c ontains n ew d ata. w hen t he c ontents o f t he sh ift register are trans ferred to the rx r register , an interrupt is generated if rie=1 in the ucr2 register . if one or more errors are detected in the received word, the appropriate receive-related fags nf , ferr, and/or perr are set within the same clock cycle. the rxif fag is clear ed when the usr register is read with rxif set, followed by a read from the rxr register, and if the rxr register has no data available. bit 1 tidle : t ransmission status 0: data transmission is in progress (data being transmitted) 1: no data transmission is in progress (transmitter is idle) the tidle flag is known as the transmission complete flag. when this read only fag i s 0, i t i ndicates t hat a t ransmission i s i n p rogress. t his fa g wi ll b e se t t o 1 when the txif fag is 1 and when there is no transmit data or break character being transmitted. when tidle is equal to 1, the tx pin becomes idle with the pin state in logic high condition. the tidle fag is cleared by reading the usr register with tidle set and then writing to the txr register . the fag is not generated when a data character or a break is queued and ready to be sent. bit 0 txif : t ransmit txr data register status 0: character is not transferred to the transmit shift register 1: character has transferred to the transmit shift register (txr data register is empty) the txif fag is the transmit data register empty fag. when this read only fag is 0, it indicat es that the character is not transferred to the transmitter shift register . when the fag is 1, it indicates that the transmitter shift register has received a character from the txr data register . the txif flag is cleared by reading the uar t status register (usr) with txif set and then writing to the txr data register . note that when t he t xen b it i s se t, t he t xif fa g b it wi ll a lso b e se t si nce t he t ransmit d ata register is not yet full.
rev. 1.00 160 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 161 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom ucr1 register the ucr1 register together with the ucr2 register are the uar t control registers that are used to set the various options for the uar t function such as overall on/of f control, parity control, data transfer bit length, etc. further explanation on each of the bits is given below. bit 7 6 5 4 3 2 1 0 name uarten bn ? pren prt st ? ps txbrk rx8 tx8 r/w r/w r/w r/w r/w r/w r/w r w p ? r 0 0 0 0 0 0 x 0 x: unknown bit 7 uarten : uart function enable control 0: disable uart; tx and rx pins are used as other pin-shared functional pins. 1: enable uart; tx and rx pins can function as uart pins defned by txen and rxen bits the uarten bit is the uart enable bit. w hen this bit is equal to 0, the uart will be disabled and the rx pin as well as the tx pin will be other pin-shared functional pins. when the bit is equal to 1, the uar t will be enabled and the tx and rx pins will function as defned by the txen and rxen enable control bits. when the uar t is disabled, it will empty the buf fer so any character remaining in the buf fer will be discarded. in addition, the value of the baud rate counter will be reset. if the uar t is disabled, all error and status fags will be reset. also the txen, rxen, txbrk, rxif, oerr, ferr, perr and nf bits will be cleared, while the tidle, txif and ridle bits will be set. other control bits in ucr1, ucr2 and brg registers will remain unaf fected. if the uar t is active and the uar ten bit is clear ed, all pending transmissions and re ceptions wi ll be terminated a nd t he module will be reset as defned above. when the uart is re-enabled, it will restart in the same confguration. bit 6 bno : number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer this bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. when this bit is equal to 1, a 9-bit data length format will be selected. if the bit is equal to 0, then an 8-bit data length format will be selected. if 9-bit data length format is selected, then bits rx8 and tx8 will be used to store the 9 th bit of the received and transmitted data respectively. bit 5 pren : parity function enable control 0: parity function is disabled 1: parity function is enabled this bit is the parity function enable bit. when this bit is equal to 1, the parity function will be enabled. if the bit is equal to 0, then the parity function will be disabled. bit 4 prt : parity type selection bit 0: even parity for parity generator 1: odd parity for parity generator this bit is the parity type selection bit. when this bit is equal to 1, odd parity type will be selected. if the bit is equal to 0, then even parity type will be selected. bit 3 stops : number of stop bits selection 0: one stop bit format is used 1: t wo stop bits format is used this bit determine s if one or two stop bits are to be used. when this bit is equal to 1, two stop bits format are used. if the bit is equal to 0, then only one stop bit format is used.
rev. 1.00 160 ??to?e? 01? ?01? rev. 1.00 161 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom bit 2 txbrk : t ransmit break character 0: no break character is transmitted 1: break characters transmit the txbrk bit is the t ransmit break chara cter bit . when thi s bit is equal to 0, there are no break characters and the tx pin operats normally . when the bit is equal to 1, t here a re t ransmit b reak c haracters a nd t he t ransmitter wi ll se nd l ogic z eros. w hen this bit is equal to 1, after the buf fered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the txbrk bit is reset. bit 1 rx8 : receive data bit 8 for 9-bit data transfer format (read only) this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9 th bit of the receive d data known as rx8. the bno bit is used to determ ine whether data transfes are in 8-bit or 9-bit format. bit 0 tx8 : t ransmit data bit 8 for 9-bit data transfer format (write only) this bit is only us ed if 9-bit data transfers are us ed, in w hich cas e this bit location will store the 9 th bit of the transmitted data known as tx8. the bno bit is used to determine whether data transfes are in 8-bit or 9-bit format. ucr2 register the ucr2 register is the second of the uar t control registers and serves several purposes. one of its main functions is to control the basic enable/disable operation if the uar t t ransmitter and receiver as well as enabling the various uar t interrupt sources. the register also serves to control the baud rate speed, receiver wake-up function enable and the address detect function enable. further explanation on each of the bits is given below. bit 7 6 5 4 3 2 1 0 name txen rxen brgh adden wake rie tiie teie r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 0 bit 7 txen : uart t ransmitter enable control 0: uart t ransmitter is disabled 1: uart t ransmitter is enabled the txen bit is the t ransmitter enable bit. when this bit is equal to 0, the transmitter will be disabled with any pending data transmissions being aborted. in addition the buf fers will be reset. in this situation the tx pin will be other pin-shared functional pin. if the txen bit is equal to 1 and the uar ten bit is also equal to 1, the transmitter will be enabled and the tx pin will be controlled by the uar t. clearing the txen bit during a transmission will cause the data transmission to be aborted and will reset the transmitter . if this situation occurs, the tx pin will be other pin-shared functional pin. bit 6 rxen : uart receiver enable control 0: uart receiver is disabled 1: uart receiver is enabled the rxen bit is the receiver enable bit. when this bit is equal to 0, the receiver will be disabled with any pending data receptions being aborted. in addition the receiver buf fers will be reset. in this situation the rx pin will be other pin-shared functional pin. if the rxen bit i s equal to 1 and t he uar ten bit i s al so equal to 1, the receiver will be enabled and the rx pin will be controlled by the uar t. clearing the rxen bit during a reception will cause the data receptio n to be aborted and will reset the receiver . if this situation occurs, the rx pin will be other pin-shared functional pin.
rev. 1.00 16 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 163 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom bit 5 brgh : baud rate speed selection 0: low speed baud rate 1: high speed baud rate the bit named brgh selects the high or low speed mode of the baud rate generator . this bit, together w ith the value placed in the baud rate regis ter, brg , controls the baud rate of the uart. if the bit is equal to 0, the low speed mode is selected. bit 4 adden : address detect function enable control 0: address detection function is disabled 1: address detection function is enabled the bit named adden is the address detection function enable control bit. when this bit is equal to 1, the address detection function is enabled. when it occurs, if the 8 th bit, which corresponds to rx7 if bno=0, or the 9 th bit, which corresponds to rx8 if bno=1, ha s a va lue of 1, t hen t he re ceived word wi ll be i dentifed a s a n a ddress, rather than data. if the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8 th or 9 th bit depending on the value of the bno bit. if the address bit known as the 8 th or 9 th bit of the received word is 0 with the address detection function being enabled, an interrupt will not be generated and the received data will be discarded. bit 3 wake : rx pin falling edge wake-up function enable control 0: rx pin wake-up function is disabled 1: rx pin wake-up function is enabled the bit enables or disables the rece iver wake-up function. if this bit is equal to 1 and the device is in idle0 or sleep mode, a falling edge on the rx pin will wake up the device. if thi s bit is equal to 0 and the device i s in the power down mode, any edge transitions on the rx pin will not wake up the device. bit 2 rie : receiver interrupt enable control 0: receiver related interrupt is disabled 1: receiver related interrupt is enabled the bit enables or disables the rece iver interrupt. if this bit is equal to 1 and when the receiver overrun flag oerr or received data available flag rxif is set, the uar t interrupt request fag will be set. if this bit is equal to 0, the uar t interrupt request fag will not be infuenced by the condition of the oerr or rxif fags. bit 1 tiie : t ransmitter idle interrupt enable control 0: t ransmitter idle interrupt is disabled 1: t ransmitter idle interrupt is enabled the bit enables or disables the transmitter idle interrupt. if this bit is equal to 1 and when t he t ransmitter i dle fa g t idle i s se t, due t o a t ransmitter i dle c ondition, t he uart interrupt request fag will be set. if this bit is equal to 0, the uar t interrupt request fag will not be infuenced by the condition of the tidle fag. bit 0 teie : t ransmitter empty interrupt enable control 0: t ransmitter empty interrupt is disabled 1: t ransmitter empty interrupt is enabled the bit enables or disables the transmitter empty interrupt. if this bit is equal to 1 and when the transmit ter empty fag txif is set, due to a transmitter empty condition, the uart interrupt request fag will be set. if this bit is equal to 0, the uar t interrupt request fag will not be infuenced by the condition of the txif fag.
rev. 1.00 16? ??to?e? 01? ?01? rev. 1.00 163 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom baud rate generator to setup the speed of the serial data communication, the uar t function contains its own dedicated baud ra te ge nerator. t he ba ud ra te i s c ontrolled by i ts own i nternal fre e runni ng 8-bi t t imer, t he period o f wh ich i s d etermined b y t wo f actors. t he f irst o f t hese i s t he v alue p laced i n t he b rg register and the second is the value of the brgh bit within the ucr2 control register . the brgh bit decides, if the baud rate generat or is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. the value in the brg register , n, which is used in the following baud rate calculation formula determines the division factor . note that n is the decimal value placed in the brg register and has a range of between 0 and 255. ucr2 brgh bit 0 1 baud rate (br) f sys [6?(n+1)] f sys [16(n+1)] by programming the brgh bit which allows selection of the related formula and programming the required value in the brg register , the required baud rate can be setup. note that because the actual baud rate is determ ined using a discrete value, n, placed in the brg register , there will be an error associated between the actual and requested value. the following example shows how the brg register value n and the error value can be calculated. brg register bit 7 6 5 4 3 2 1 0 name brg7 brg6 brg5 brg ? brg3 brg ? brg1 brg0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r x x x x x x x x x: unknown bit 7~0 brg7~brg0 : baud rate values by programming the brgh bit in the ucr2 register which allows selection of the related formula described above and programming the required value in the brg register, the required baud rate can be setup. calculating the baud rate and error values for a clock frequency of 4mhz, and with brgh set to 0 determine the brg register value n, the actual baud rate and the error value for a desired baud rate of 4800. from the above table the desired baud rate br = [64(n+1)] re-arranging this equation gives n = (br64) - 1 giving a value for n = (480064) - 1 = 12.0208 to obtain the closest value, a decim al value of 12 should be placed into the brg register . this gives an actual or calculated baud rate value of br = [64(12+1)] = 4808 therefore the error is equal to 4808-4800 4800 = 0.16%
rev. 1.00 16 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 165 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom uart setup and control for data transfer , the uar t functio n utilizes a non-return-to-zero, more commonly known as nrz, format. this is compos ed of one s tart bit, eight or nine data bits and one or tw o s top bits . p arity is supporte d by t he uar t hardwa re and ca n be se tup t o be eve n, odd or no pari ty. for the m ost common data format, 8 data bits along with no parity and one stop bit, denoted as 8, n, 1, is used as the default setti ng, which is the setting at power -on. the number of data bits and stop bits, along with the parity , are setup by programming the corresponding bno, pr t, pren and st ops bits in the ucr1 register . the baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator , while the data is transmitted and received lsb frst. although the transmitter and receiver of the uart are functionally independent, they both use the same data format and baud rate. in all cases stop bits will be used for data transmission. enabling/disabling the uart interface the basic on/of f function of the internal uar t function is controlled using the uar ten bit in the ucr1 register . if the uar ten, txen and rxen bits are set, then these two uar t pins will act as n ormal t x o utput p in a nd r x i nput p in r espectively. i f n o d ata i s b eing t ransmitted o n t he t x pin, then it will default to a logic high value. clearing the uar ten bit will disable the tx and rx pins and these two pins will be used as i/ o or ot her pi n-shared func tional pi ns. w hen t he uar t func tion i s di sabled, t he buf fer wi ll be reset to an empty condition, at the same time discarding any remaining residual data. disabling the uart will also reset the enable control, the error and status fags with bits txen, rxen, txbrk, rxif, oe rr, fe rr, pe rr and nf bei ng cl eared whi le bi ts t idle, t xif and ridle wi ll be set. the remaining control bits in the ucr1, ucr2 and brg registers will remain unaf fected. if the uar ten bit in the ucr1 regi ster is cle ared while the uar t is act ive, then al l pendi ng transmissions and receptions will be immediately suspended and the uar t will be reset to a condition as defned above. if the uar t is then subsequently re-enabled, it will restart again in the same confguration. data, parity and stop bit selection the f ormat o f t he d ata t o b e t ransferred i s c omposed o f v arious f actors su ch a s d ata b it l ength, parity on/of f, parity type, address bits and the number of stop bits. these factors are determined by the setup of various bits within the ucr1 register . the bno bit controls the number of data bits which can be set to either 8 or 9. the pr t bit controls the choice if odd or even parity . the pren bit controls the parity on/of f function. the st ops bit decides whether one or two stop bits are to be used. the following table shows various formats for data transmission. the address detect mode control bit identif es the frame as an address character . the number of stop bits, which can be either one or two, is independent of the data length. start bit data bits address bits parity bit stop bit example of 8-bit data formats 1 8 0 0 1 1 7 0 1 1 1 7 1 0 1 example of 9-bit data formats 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 transmitter receiver data format
rev. 1.00 16? ??to?e? 01? ?01? rev. 1.00 165 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom the following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats.

uart transmitter data word lengths of either 8 or 9 bits can be selected by programming the bno bit in the ucr1 register. w hen b no b it i s se t, t he wo rd l ength wi ll b e se t t o 9 b its. i n t his c ase t he 9 th b it, wh ich is the msb, needs to be stored in the tx8 bit in the ucr1 register . at the transmitter core lies the transmitter shift register , more commonly known as the tsr, whos e data is obtained from the transmit d ata r egister, wh ich i s k nown a s t he t xr r egister. t he d ata t o b e t ransmitted i s l oaded into this txr register by the applic ation program. the tsr register is not written to with new data until the stop bit from the previous transmission has been sent out. as soon as this stop bit has been transmitted, the tsr can then be loaded with new data from the txr register , if it is available. it should be noted that the tsr register , unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. an actual transmission of data will normally be enabled when the txen bit is set, but the data will not be transmitted until the txr register has been loaded with data and the baud rate generator ha s de fned a shi ft c lock sourc e. however , t he t ransmission c an a lso be i nitiated by frst loading data into the txr register , after which the txen bit can be set. when a transmission of data begins, the tsr is normally empty , in which case a transfer to the txr register will result in an immed iate transfer to the tsr. if during a transmission the txen bit is cleared, the transmission will imm ediately cease and the transmitter will be reset. the tx output pin will then return to the i/ o or other pin-shared function. transmitting data when the uar t is transmitting data, the data is shifted on the tx pin from the shift register , with the least signifcant bit lsb frst. in the transmit mode, the txr register forms a buf fer between the internal bus and the transmitter shift register . it should be noted that if 9-bit data format has been selected, then the msb will be take n from the tx8 bit in the ucr1 register . the steps to initiate a data transfer can be summarized as follows: ? make the correct selection of the bno, pr t, pren and st ops bits to defne the required word length, parity type and number of stop bits. ? setup the brg register to select the desired baud rate. ? set the txe n bit to ensure that the uar t transmit ter is enabled and the tx pin is used as a uart transmitter pin. ? access the usr register and write the data that is to be transmitted into the txr register . note that this step will clear the txif bit. this sequence of events can now be repeated to send additional data. it should be noted that when txif=0, data will be inhibited from being written to the txr register . clearing the txif fag is always achieved using the following software sequence:
rev. 1.00 166 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 167 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom 1. a usr register access 2. a txr register write execution the read-only txif fag is set by the uar t hardware and if set indic ates that the txr register is empty and that other data can now be written into the txr register without overwriting the previous data. if the teie bit is set, then the txif fag will generate an interrupt. during a data transmission, a write instruction to the txr register will place the data into the txr register , which will be copied to the shift register at the end of the present transmission. when there is no data transmission in progress, a write instruction to the txr register will place the data directly into the shift register , resulting in the commencement of data transmission, and the txif bit being immediately set. when a frame transmission is complete, which happens after stop bits are sent or after the break frame, the tidle bit will be set. t o clear the tidle bit the following software sequence is used: 1. a usr register access 2. a txr register write execution note that both the txif and tidle bits are cleared by the same software sequence. transmitting break if the txbrk bit is set, then the break characters will be sent on the next transmission. break character t ransmission c onsists o f a st art b it, f ollowed b y 1 3xn 0 b its, wh ere n= 1, 2 , e tc. i f a break character is to be transmitted, then the txbrk bit must be frst set by the application program and then cleared to generate the stop bits. t ransmitting a break character will not generate a transmit interrupt. note that a break condition length is at least 13 bits long. if the txbrk bit is continually kept a t a l ogic hi gh l evel, t hen t he t ransmitter c ircuitry wi ll t ransmit c ontinuous bre ak c haracters. after the application program has cleared the txbrk bit, the transmitter will fnish transmitting the last break character and subsequently send out one or two stop bits. the automatic logic high at the end of the last break character will ensure that the start bit of the next frame is recognized. uart receiver the uart is capable of receiving word lengths of either 8 or 9 bits can be selected by programming the bno bit in the ucr1 register . when bno bit is set, the word length will be set to 9 bits. in this c ase t he 9 th b it, wh ich i s t he msb , wi ll b e st ored i n t he r x8 b it i n t he uc r1 r egister. at t he receiver core lies the receiver shift register more commonly known as the rsr. the data which is receive d on the rx external input pin is sent to the data recovery block. the data recovery block operating speed is 16 times that of the baud rate, while the main receiv e serial shifter operates at the baud rate. after the rx pin is sampled for the stop bit, the received data in rsr is transferred to the receive data register, if the register is empty. the data which is received on the external rx input pin is sample d three times by a majority detect circuit to determine the logic level that has been placed onto the rx pin. it should be noted that the rsr register , unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. receiving data when the uar t receiver is receiv ing data, the data is serially shifted in on the external rx input pin to the shift register , with the lea st signifcant bit lsb frst. the rxr register is a two byte deep fifo data buf fer, w here tw o bytes can be held in the f ifo w hile the 3 rd byte can continue to be received. note that the application program must ensure that the data is read from rxr before the 3 rd byte has been completely shifted in, otherwise the 3 rd byte will be discarded and an overrun error oerr will be subsequently indicated. the steps to initiate a data transfer can be summarized as follows:
rev. 1.00 166 ??to?e? 01? ?01? rev. 1.00 167 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom ? make the correct selection of the bno, pr t, pren and st ops bits to defne the required word length, parity type and number of stop bits. ? setup the brg register to select the desired baud rate. ? set the rxen bit to ensure that the uar t receiver is enabled and the rx pin is used as a uar t receiver pin. at this point the receiver will be enabled which will begin to look for a start bit. when a character is received, the following sequence of events will occur: ? the rxif bit in the usr register will be set then rxr register has data available, at least one more character can be read. ? when the content s of the shift register have been transferred to the rxr register and if the rie bit is set, then an interrupt will be generated. ? if during reception, a frame error , noise error , parity error or an overrun error has been detected, then the error fags can be set. the rxif bit can be cleared using the following software sequence: 1. a usr register access 2. a rxr register read execution receiving break any break character received by the uar t will be managed as a framing error . the receiver will count and expect a certain number of bit times as specifed by the value s programmed into the bno and st ops bits. if the break is much longer than 13 bit times, the reception will be considered as complete a fter t he num ber of bi t t imes spe cifed by bno a nd st ops. t he rxif bi t i s se t, fe rr is set, zeros are loaded into the rece ive data register , interrupts are generated if appropriate and the ridle bit is set. if a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the ferr fag, the receiver must wait for a valid stop bit before looking for the next start bit. the receiver will not make the ass umption that the break condition on the line is the next start bit. a break is regarded as a character that contains only zeros with the ferr fag set. the break character will be loaded into the buf fer and no further data will be received until stop bits are received. it should be noted that the ridle read only fag will go high when the stop bits have not yet been received. the reception of a break character on the uar t registers will result in the following: ? the framing error fag, ferr, will be set. ? the receive data register, rxr, will be cleared. ? the oerr, nf, perr, ridle or rxif fags will possibly be set. idle status when the receiver is reading data, which means it will be in between the detection of a start bit and the readin g of a stop bit, the receiver status fag in the usr register , otherwise known as the ridle fag, will have a zero value. in between the reception of a stop bit and the detection of the next start bit, the ridle fag will have a high value, which indicates the receiver is in an idle condition. receiver interrupt the re ad onl y re ceive i nterrupt fa g, rxif , i n t he usr re gister i s se t by a n e dge ge nerated by t he receiver. an i nterrupt i s ge nerated i f rie =1, whe n a word i s t ransferred from t he re ceive shi ft register, rsr, to the receive data register , rxr. an overrun error can also generate an interrupt if rie=1.
rev. 1.00 168 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 169 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom managing receiver errors several types of reception errors can occur within the uart module, the following section describes the various types and how they are managed by the uart. overrun error C oerr the rxr register is composed of a two byte deep fifo data buf fer, where two bytes can be held in the fifo register , while a 3 th byte can continue to be received. before the 3 th byte has been entirely shifted in, the data should be read from the rxr register . if this is not done, the overrun error fag oerr will be consequently indicated. in the event of an overrun error occurring, the following will happen: ? the oerr fag in the usr register will be set. ? the rxr contents will not be lost. ? the shift register will be overwritten. ? an interrupt will be generated if the rie bit is set. the o err flag can be cleared by an acces s to the u sr regis ter follow ed by a read to the rx r register. noise error C nf over-sampling i s u sed f or d ata r ecovery t o i dentify v alid i ncoming d ata a nd n oise. i f n oise i s detected within a frame, the following will occur: ? the read only noise fag, nf, in the usr register will be set on the rising edge of the rxif bit. ? data will be transferred from the shift register to the rxr register. ? no interrupt will be generated. however this bit rises at the same time as the rxif bit which itself generates an interrupt. note t hat t he nf fa g i s r eset b y a usr r egister r ead o peration f ollowed b y a n r xr r egister r ead operation. framing error C ferr the read only framing error fag, ferr, in the usr register , is set if a zero is detected instead of stop bits. if two stop bits are selecte d, both stop bits must be high. otherwise the ferr fag will be set. the ferr fag is buffered along with the received data and is cleared in any reset. parity error C perr the read only parity error fag, perr, in the usr register , is set if the parity of the received word is incorrect. this error fag is only applicable if the parity function is enabled, pren=1, and if the parity type, odd or even, is s elected. the read only p err f ag is buf fered along w ith the received data bytes. it is cleared on any reset, it should be noted that the ferr and perr fags are buf fered along with the corresponding word and should be read before reading the data word.
rev. 1.00 168 ??to?e? 01? ?01? rev. 1.00 169 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom uart interrupt structure several i ndividual uar t c onditions c an ge nerate a uar t i nterrupt. w hen t hese c onditions e xist, a low pulse will be generated to get the attention of the microcontroller . these conditions are a transmitter data register empty , trans mitter idle, receiver data available, receiver overrun, addres s detect and an rx pin wake-up. when any of these conditions are created, if its corresponding interrupt cont rol is enabled and the stac k is not ful l, the progra m wil l jump to it s corresponding interrupt vector w here it can be serviced before returning to the main program. four of thes e conditions h ave t he c orresponding usr r egister fa gs wh ich wi ll g enerate a uar t i nterrupt i f i ts associated interrupt enable control bit in the ucr2 register is set. the two transmitter interrupt conditions have their own corresponding enable control bits, while the two receiver interrupt conditions have a shared enable control bit. these enable bits can be used to mask out individual uart interrupt sources. the address det ect condit ion, whi ch i s al so a uar t i nterrupt source, does not have an associa ted flag, but will generate a uar t interrupt when an address detect condition occurs if its function is e nabled by se tting t he adde n bi t i n t he ucr2 re gister. an rx pi n wa ke-up, whi ch i s a lso a uart interrupt source, does not have an associated fag, but will generate a uar t interrupt if the microcontroller i s woke n up from idl e0 or sl eep m ode by a fa lling e dge on t he rx pi n, i f t he wake and rie bits in the ucr2 register are set. note that in the event of an rx wake-up interrupt occurring, there will be a certain period of delay , commonly known as the system start-up t ime, for the oscillator to restart and stabilize before the system resumes normal operation. note t hat t he usr r egister f lags a re r ead o nly a nd c annot b e c leared o r se t b y t he a pplication program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the cas e for some of the other interrupts. the flags will be cleared automatically whe n c ertain a ctions a re t aken by t he uar t, t he de tails of whi ch a re gi ven i n t he uart regi ster se ction. the overal l uar t i nterrupt ca n be disable d or ena bled by t he rel ated interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the uart module is masked out or allowed. usr registe? t?ansmitte? empty flag txif 0 1 wake inte??upt signal to mcu t?ansmitte? idle flag tidle re?eive? ?ve??un flag oerr re?eive? data availa?le rxif rx pin wake-up ucr? registe? or 0 1 adden 0 1 rie 0 1 tiie 0 1 teie 0 1 rx7 if bn?=0 rx8 if bn?=1 ucr? registe? uart inte??upt request flag urf 0 1 ure 0 1 emi uart interrupt structure
rev. 1.00 170 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 171 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom address detect mode setting the address detect function enable control bit, adden, in the ucr2 register , enables this special function. if this bit is set to 1, then an additional qualifer will be placed on the generation of a re ceiver da ta a vailable i nterrupt, whi ch i s re quested by t he rxif fl ag. if t he adde n bi t is equal to 1, then w hen the data is available, an interrupt w ill only be generated, if the highest received bit has a high value. note that the related interrupt enable control bit and the emi bit of the microcontroller must also be enabled for correct interrupt generation. the highest address bit is the 9 th bit if the bit bno=1 or the 8 th bit if the bit bno=0. if the highest bit is high, then the received word wi ll be de fned a s a n a ddress ra ther t han da ta. a da ta a vailable i nterrupt wi ll be ge nerated every tim e the last bit of the receiv ed word is set. if the adden bit is equal to 0, then a receive data a vailable interrupt will be generated each time the rxif fag is set, irrespective of the data last but status. the address detection and parity functions are mutually exclusive functions. therefore, if the address detect function is enable d, then to ensure correct operation, the parity function should be disabled by resetting the parity function enable bit pren to zero. adden bit 9 if bno=1 bit 8 if bno=0 uart interrupt generated 0 0 1 1 0 x 1 adden bit function uart power down and wake-up when the mcu system clock is switched of f, the uar t will cease to function. if the mcu executes the hal t instruction and switches of f the system clock while a transmission is still in progress, then the transmission will be paused until the uar t clock source derived from the microcontroller is activated. in a similar way , if the mcu executes the hal t instruction and switches of f the system clock w hile receiving data, then the reception of data w ill likewise be paus ed. when the mcu enters the idle or sleep mode, note that the usr, ucr1, ucr2, transmit and receive registers, as well as the brg register will not be af fected. it is recomm ended to make sure frst that the uar t data transmission or reception has been finished before the microcontroller enters the power down mode. the ua rt function contains a receiver rx pin wake-up function, which is enabled or disabled by the w ake bit in the ucr2 register . if this bit, along with the uar t enable bit, uar ten, the receiver enable bit, rxen and the receiver interrupt bit, rie, are all set before the mcu enters the idle0 or sleep mode, then a fall ing edge on the rx pin will wake up the mcu from the idle0 or sl eep mo de. no te t hat a s i t t akes c ertain sy stem c lock c ycles a fter a wa ke-up, b efore n ormal microcontroller operation resumes, any data received during this time on the rx pin will be ignored. for a uar t wake-up interrupt to occur , in addition to the bits for the wake-up being set, the global interrupt enable bit, emi, and the uart interrupt enable bit, ure, must be set. if the emi and ure bits are not set then only a wake up event will occur and no interrupt will be generated. note also that as it takes certain system clock cycles after a wake-up before normal microcontroller resumes, the uart interrupt will not be generated until after this time has elapsed.
rev. 1.00 170 ??to?e? 01? ?01? rev. 1.00 171 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom low voltage detector C lvd each device has a low v oltage detector function, also known as l vd. this enabled the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low v oltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name l vdc. three bits in this register , vl vd2~vlvd0, are used to select one of eight fxed voltages below which a l ow vo ltage c ondition wi ll be de termined. a l ow vo ltage c ondition i s i ndicated whe n t he l vdo bit is set. if the l vdo bit is low , this indicates that the v dd voltage is above the preset low voltage value. the l vden bit is used to control the overall on/of f function of the low voltage detector . setting the bit high will enable the low voltage detector . clearing the bit to zero will switch of f the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch of f the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 name lvd ? lvden vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w p ? r 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 : lvd output fag 0: no low v oltage detected 1: low v oltage detected bit 4 : low v oltage detector enable control 0: disable 1: enable bit 3 unimplemented, read as 0 bit 2~0 : lvd v oltage selection 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.0v
rev. 1.00 17 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 173 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom lvd operation the low v oltage detector function operates by comparing the power supply voltage, v dd , with a pre-specifed volta ge level stored in the l vdc register . this has a range of between 2.0v and 4.0v . when the power supply voltage, v dd , falls below this pre-determined value, the l vdo bit will be set high indicating a low power supply voltage condition. the low v oltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the l vden bit is high. after enabling the low voltage detector , a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly , at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. lvd operation the low v oltage detector also has its own interrupt which is contained within one of the multi- function interrupts, providing an alternative means of low voltage detection, in addition to polling the l vdo bit. the interrupt will only be generated after a delay of t lvd after the l vdo bit has been set high by a low voltage condition. when the device is powered down the low v oltage detector will rema in active if the l vden bit is high. in this case, the l vf interrupt request fag will be set, causing an interru pt to be generated if v dd falls below the preset l vd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low v oltage detector wake up function is not required then the lvf fag should be frst set high before the device enters the sleep or idle mode.
rev. 1.00 17? ??to?e? 01? ?01? rev. 1.00 173 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t imer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. these devices contain several external interrupt and internal interrupts functions . the external interrupts are generated by the action of the external int0 and int1 pins, while the internal interrupts are generated by various internal functions such as the tms, t ime base, lvd, eeprom, sim, uart and the a/d converter, etc. interrupt registers overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is control led by a series of registers, located in the special purpose data memory , as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. t he frst i s t he int c0~intc2 re gisters whi ch se tup t he pri mary i nterrupts, t he se cond is the mfi0~mfi2 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each register contains a number of enable bits to enable or disable individual interrupts as well as i nterrupt fa gs t o i ndicate t he p resence o f a n i nterrupt r equest. t he n aming c onvention o f t hese follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes glo ? al emi intn pins intne intnf n = 0 ~ 1 multi-fun ? tion mfne mfnf n = 0~ ? a/d conve ? te ? ade adf time base tbne tbnf n = 0 ~ 1 sim sime simf lvd lve lvf eepr ? m w ? ite ope ? ation dee def tm tnpe tnpf n = 0~1 tnae tnaf n = 0~1 interrupt register bit naming conventions C HT66F0175 function enable bit request flag notes glo ? al emi intn pins intne intnf n = 0 ~ 1 compa ? ato ? cpe cpf multi-fun ? tion mfne mfnf n = 0~ ? a/d conve ? te ? ade adf time base tbne tbnf n = 0 ~ 1 sim sime simf uart ure urf lvd lve lvf eepr ? m w ? ite ope ? ation dee def tm tnpe tnpf n = 0~ ? tnae tnaf n = 0~ ? interrupt register bit naming conventions C ht66f0185
rev. 1.00 17 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 175 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom register name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 mf0f int0f mf0e int0e emi intc1 tb0f adf mf ? f mf1f tb0e ade mf ? e mf1e intc ? simf int1f tb1f sime int1e tb1e mfi0 t0af t0pf t0ae t0pe mfi1 t1af t1pf t1ae t1pe mfi3 def lvf dee lve interrupt registers list C HT66F0175 register name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 mf0f cpf int0f mf0e cpe int0e emi intc1 tb0f adf mf ? f mf1f tb0e ade mf ? e mf1e intc ? urf simf int1f tb1f ure sime int1e tb1e mfi0 t0af t0pf t0ae t0pe mfi1 t ? af t ? pf t1af t1pf t ? ae t ? pe t1ae t1pe mfi3 def lvf dee lve interrupt registers list C ht66f0185 integ register bit 7 6 5 4 3 2 1 0 name int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w p ? r 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3~2 int1s1~int1s0 : interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 1~0 int0s1~int0s0 : interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges
rev. 1.00 17? ??to?e? 01? ?01? rev. 1.00 175 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom intc0 register C HT66F0175 bit 7 6 5 4 3 2 1 0 name mf0f int0f mf0e int0e emi r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 mf0f : multi-function 0 interrupt request fag 0: no request 1: interrupt request bit 5 unimplemented, read as 0 bit 4 int0f : int0 interrupt request fag 0: no request 1: interrupt request bit 3 mf0e : multi-function 0 interrupt control 0: disable 1: enable bit 2 unimplemented, read as 0 bit 1 int0e : int0 interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable intc0 register C ht66f0185 bit 7 6 5 4 3 2 1 0 name mf0f cpf int0f mf0e cpe int0e emi r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 mf0f : multi-function 0 interrupt request fag 0: no request 1: interrupt request bit 5 cpf : comparator interrupt request fag 0: no request 1: interrupt request bit 4 int0f : int0 interrupt request fag 0: no request 1: interrupt request bit 3 mf0e : multi-function 0 interrupt control 0: disable 1: enable bit 2 cpe : comparator interrupt control 0: disable 1: enable bit 1 int0e : int0 interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable
rev. 1.00 176 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 177 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom intc1 register bit 7 6 5 4 3 2 1 0 name tb0f adf mf ? f mf1f tb0e ade mf ? e mf1e r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 0 bit 7 tb0f : t ime base 0 interrupt request fag 0: no request 1: interrupt request bit 6 adf : a/d converter interrupt request fag 0: no request 1: interrupt request bit 5 mf2f : multi-function 2 interrupt request fag 0: no request 1: interrupt request bit 4 mf1f : multi-function 1 interrupt request fag 0: no request 1: interrupt request bit 3 tb0e : t ime base 0 interrupt control 0: disable 1: enable bit 2 ade : a/d converter interrupt control 0: disable 1: enable bit 1 mf2e : multi-function 2 interrupt control 0: disable 1: enable bit 0 mf1e : multi-function 1 interrupt control 0: disable 1: enable
rev. 1.00 176 ??to?e? 01? ?01? rev. 1.00 177 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom intc2 register C HT66F0175 bit 7 6 5 4 3 2 1 0 name simf int1f tb1f sime int1e tb1e r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 simf : sim interrupt request fag 0: no request 1: interrupt request bit 5 int1f : int1 interrupt request fag 0: no request 1: interrupt request bit 4 tb1f : t ime base 1 interrupt request fag 0: no request 1: interrupt request bit 3 unimplemented, read as 0 bit 2 sime : sim interrupt control 0: disable 1: enable bit 1 int1e : int1 interrupt control 0: disable 1: enable bit 0 tb1e : t ime base 1 interrupt control 0: disable 1: enable
rev. 1.00 178 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 179 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom intc2 register C ht66f0185 bit 7 6 5 4 3 2 1 0 name urf simf int1f tb1f ure sime int1e tb1e r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 0 bit 7 urf : uart interrupt request fag 0: no request 1: interrupt request bit 6 simf : sim interrupt request fag 0: no request 1: interrupt request bit 5 int1f : int1 interrupt request fag 0: no request 1: interrupt request bit 4 tb1f : t ime base 1 interrupt request fag 0: no request 1: interrupt request bit 3 ure : uart interrupt control 0: disable 1: enable bit 2 sime : sim interrupt control 0: disable 1: enable bit 1 int1e : int1 interrupt control 0: disable 1: enable bit 0 tb1e : t ime base 1 interrupt control 0: disable 1: enable mfi0 register bit 7 6 5 4 3 2 1 0 name t0af t0pf t0ae t0pe r/w r/w r/w r/w r/w p ? r 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 t0af : tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t0pf : tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t0ae : tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe : tm0 comparator p match interrupt control 0: disable 1: enable
rev. 1.00 178 ??to?e? 01? ?01? rev. 1.00 179 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom mfi1 register C HT66F0175 bit 7 6 5 4 3 2 1 0 name t1af t1pf t1ae t1pe r/w r/w r/w r/w r/w p ? r 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 t1af : tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t1pf : tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t1ae : tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe : tm1 comparator p match interrupt control 0: disable 1: enable mfi1 register C ht66f0185 bit 7 6 5 4 3 2 1 0 name t ? af t ? pf t1af t1pf t ? ae t ? pe t1ae t1pe r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 0 0 0 0 0 0 bit 7 t2af : tm2 comparator a match interrupt request fag 0: no request 1: interrupt request bit 6 t2pf : tm2 comparator p match interrupt request fag 0: no request 1: interrupt request bit 5 t1af : tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t1pf : tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 t2ae : tm2 comparator a match interrupt control 0: disable 1: enable bit 2 t2pe : tm2 comparator p match interrupt control 0: disable 1: enable bit 1 t1ae : tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe : tm1 comparator p match interrupt control 0: disable 1: enable
rev. 1.00 180 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 181 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom mfi2 register bit 7 6 5 4 3 2 1 0 name def lvf dee lve r/w r/w r/w r/w r/w p ? r 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 def : data eeprom interrupt request fag 0: no request 1: interrupt request bit 4 lvf : lvd interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 dee : data eeprom interrupt control 0: disable 1: enable bit 0 lve : lvd interrupt control 0: disable 1: enable interrupt operation when the conditions for an interrupt event occur, such as a tm comparator p or comparator a or a/d conversion compl etion, etc, the rele vant interrupt request fag will be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enabl e bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti, which retrieves the original program counter address from the stack and allow s the microcontroller to continue w ith normal execution at the point w here the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . o nce an interrupt subroutine is serviced, all other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request fag will still be recorded.
rev. 1.00 180 ??to?e? 01? ?01? rev. 1.00 181 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. al l o f t he i nterrupt r equest fa gs wh en se t wi ll wa ke-up t he d evice i f i t i s i n sl eep o r idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode. int0 pin int1 pin int0f int1f int0e int1e emi 0?h emi m. fun?t. 0 mf0f mf0e emi 0ch emi 10h 1?h time base 0 tb0f tb0e emi 18h lvd lvf lve emi 1ch inte??upt name request flags ena?le bits maste? ena?le vector emi auto disa?led in isr p?io?ity high low m. fun?t. 1 mf1f mf1e tm0 p t0pf t0pe tm0 a t0af t0ae inte??upts ?ontained within multi-fun?tion inte??upts xxe ena?le bits xxf request flag? auto ?eset in isr legend xxf request flag? no auto ?eset in isr emi ?0h a/d adf ade emi ??h m. fun?t. ? mf?f mf?e time base 1 tb1f tb1e tm1 p t1pe tm1 a t1ae eepr?m def dee sim simf sime emi ?8h t1pf t1af interrupt scheme C HT66F0175 int0 pin int1 pin int0f int1f int0e int1e emi 0?h emi 08h m. fun?t. 0 mf0f mf0e emi 0ch emi 10h 1?h time base 0 tb0f tb0e emi 18h lvd lvf lve emi 1ch inte??upt name request flags ena?le bits maste? ena?le vector emi auto disa?led in isr p?io?ity high low m. fun?t. 1 mf1f mf1e tm0 p t0pf t0pe tm0 a t0af t0ae inte??upts ?ontained within multi-fun?tion inte??upts xxe ena?le bits xxf request flag? auto ?eset in isr legend xxf request flag? no auto ?eset in isr emi ?0h a/d adf ade emi ??h m. fun?t. ? mf?f mf?e time base 1 tb1f tb1e tm1 p t1pe tm1 a t1ae eepr?m def dee tm? p t?pe tm? a t?ae emi compa?ato? cpf cpe sim simf sime emi ?8h t1pf t1af t?pf t?af uart urf ure emi ?ch interrupt scheme C ht66f0185
rev. 1.00 18 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 183 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom external interrupt the external interrupts are controlled by signal transitions on the pins int0~int1. an external interrupt request will take place when the external interrupt request fags, int0f~int1f , are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins . t o allow the program to branch to its res pective interrupt vector addres s, the g lobal i nterrupt e nable b it, e mi, a nd r espective e xternal i nterrupt e nable b it, i nt0e~int1e, must first be set. additionally the correct interrupt edge type mus t be selected using the integ register to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be confgured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set and the external interrupt pin is selected by the corresponding pin-shared function selection bits. the pin must also be setup as an input by setting the corresponding bit in the port control register . when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector , will take place. when the interrupt is serviced, the external interrupt request fags, int0f~int1f , will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function. comparator interrupt C ht66f0185 the comparator interrupt is controlled by the internal comparator . a comparator interrupt request will take place when the comparator interrupt request fag, cpf , is set, a situation that will occur when the comparator output changes state. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and comparator interrupt enable bit, cpe, must frst b e se t. w hen t he i nterrupt i s e nabled, t he st ack i s n ot f ull a nd t he c omparator i nputs g enerate a compar ator output transition, a subroutine call to the comparator inte rrupt vector , will take place. when the interrup t is serviced, the comparator interrupt request fag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. multi-function interrupt within the device there are up to three multi-function interrupts . unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the tm interrupts, lvd interrupt and eeprom write operation interrupt. a multi-function interrupt request will take place when any of the multi-function interrupt request flags mfnf are set. the multi-function interrupt flags will be set when any of their included functions generate an interrupt request fag. t o allow the program to branch to its respective interrupt vector address, when the multi-func tion interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi- function request fag will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, it must be noted that, although the multi-function interrupt request flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the multi-function interrupts will not be automatically reset and must be manually reset by the application program.
rev. 1.00 18? ??to?e? 01? ?01? rev. 1.00 183 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom a/d converter interrupt the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, adf , is set, which occurs when the a/d conversion process fnishes. t o allow the program to branch to its respective interrupt vector a ddress, the global interrupt enable bit, emi, a nd a/ d interrupt enable bit, ade, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector , will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. time base interrupt the function of the t ime base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. t o allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and t ime base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the t ime base overfow s, a subroutine call to their res pective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f , will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider , the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the t ime base interrupt period, can originate from several different sources, as shown in the system operating mode section. m u x f sys /? f tbc p?es?ale? tbck f tb f tb /? 8 ~ f tb /? 15 m u x tb11~tb10 time base 0 inte??upt time base 1 inte??upt tb0?~tb00 p?es?ale? m u x f tb /? 1? ~ f tb /? 15 time base interrupts
rev. 1.00 18 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 185 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom tb0c register bit 7 6 5 4 3 2 1 0 name tb ? n tbck tb11 tb10 lxtlp tb0 ? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w r/w p ? r 0 0 1 1 0 1 1 1 bit 7 tb0on : t ime base function enable control 0: disable 1: enable bit 6 tbck : t ime base clock source select 0: f tbc 1: f /4 bit 5~4 tb11~tb10 : t ime base 1 time-out period selection 00: 2 /f tb 01: 2 13 /f tb 10: 2 /f tb 11: 2 /f tb bit 3 lxtlp : lxt low power control 0: disable C lxt quick start-up 1: enable C lxt slow start-up bit 2~0 tb02~tb00 : t ime base 0 time-out period selection 000: 2 8 /f tb 001: 2 9 /f tb 010: 2 /f tb 011: 2 /f tb 100: 2 /f tb 101: 2 13 /f tb 110: 2 /f tb 111: 2 /f tb serial interface module interrupt the serial interface module interrupt, also known as the sim interrupt, is controlled by the spi or c data transfer . a sim interrupt request will take place when the sim interrupt request fag, simf , is set, which occurs when a byte of data has been received or transmitted by the sim interface, an i c slave address match or i c bus time-out occurrence. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi and the serial interface interrupt enable bit, sime, must frst be set. when the interrupt is enabled, the stack is not full and any of the above described situations occurs, a subroutine call to the respective sim interrupt vector, will t ake p lace. w hen t he se rial i nterface i nterrupt i s se rviced, t he e mi b it wi ll b e a utomatically cleared to disable other interrupts. the simf fag will also be automatically cleared. uart transfer interrupt C ht66f0185 the uar t t ransfer interrupt is controlled by several uar t transfer conditions. when one of these conditions occurs, an interrupt pulse will be generated to get the attention of the microcontroller . these conditions are a transmitter data register empty , transmitter idle, receiver data available, receiver overrun, address detect and an rx pin wake-up. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and uar t interrupt enable bit, ure, must frst be set. when the interrupt is enabled, the stack is not full and any of the conditions described above occurs, a subroutine call to the uar t interrupt vector , will take place. when the interrupt is serviced, the uar t interrupt fag, urf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts.
rev. 1.00 18? ??to?e? 01? ?01? rev. 1.00 185 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom lvd interrupt the l ow v oltage de tector i nterrupt i s c ontained wi thin t he mu lti-function i nterrupt. an l vd interrupt reques t w ill take place w hen the l vd interrupt request flag, l vf, is s et, w hich occurs when the low v oltage detector function detects a low power supply voltage. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, low v oltage interrupt enable bit, l ve, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage conditio n occurs, a subroutine call to the multi-function interrupt vector , will take place. when the low v oltage interrupt is serviced, the emi bit will be automatically clear ed to disable other interrupts. however , only the multi-function interrupt request fag will be also automatically cleared. as the l vf fag will not be automatically cleared, it has to be cleared by the application program. eeprom interrupt the eeprom w rite interrupt is contained within the multi-function interrupt. an eeprom write interrupt request will take place when the eeprom w rite interrupt request fag, def , is set, which occurs when an eeprom w rite cycle ends. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, eeprom w rite interrupt enable bit, dee, and associated multi-function interrupt enable bit must first be set. when the interrupt is enabled, the stack is not full and an eeprom w rite cycle ends, a subroutine call to the respective multi-function interrupt vector will take place. when the eeprom w rite interrupt is serviced, the emi bit will be automatically clear ed to disable other interrupts. however , only the multi-function interrupt request flag will be automatically cleared. as the def flag will not be automatically cleared, it has to be cleared by the application program. tm interrupt the compact, standard and periodic tms have two interrupts, one comes from the comparator a match situation and the other comes from the comparator p match situation. all of the tm interrupts are contained within the multi-function interrupts. for all of the tm types there are two interrupt request fa gs and two enable control bit s. a tm int errupt reque st wi ll ta ke plac e when any of the tm re quest fa gs a re se t, a si tuation whi ch oc curs whe n a t m c omparator p or a m atch si tuation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts. however , only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program.
rev. 1.00 186 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 187 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom interrupt wake-up function each of the int errupt funct ions has the ca pability of waki ng up the mi crocontroller when in the sleep o r i dle mo de. a wa ke-up i s g enerated wh en a n i nterrupt r equest fa g c hanges f rom l ow to high and is independent of whether the interrupt is enabled or not. therefore, even though these devices are in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their re spective interrupt fl ag to be set hi gh and consequently ge nerate an i nterrupt. c are m ust t herefore b e t aken i f sp urious wa ke-up si tuations a re t o b e a voided. i f a n interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interr upt enable bits have no ef fect on the interrupt wake-up function. programming considerations by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained w ithin a m ulti-function interrupt, then w hen the interrupt service routine is executed, as only the multi-function interrupt request flags, mfnf , will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is in the sleep or idle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.00 186 ??to?e? 01? ?01? rev. 1.00 187 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom confguration options confguration options refer to certa in options within the mcu that are programmed into the device during the programming process. during the development process, these options are selected using the ht -ide software development tools. as these options are programmed into the device using the hardwa re programm ing tools, once they are sel ected they cannot be changed la ter using the application program. all options must be defned for proper system function, the details of which are shown in the table. no. options 1 high speed system ? s ? illato ? sele ? tion f h C hxt o ? hirc ? low speed system ? s ? illato ? sele ? tion f sub C lxt o ? lirc 3 hirc f ? equen ? y sele ? tion f hirc C 8mhz ? 1 ? mhz o ? 16mhz application circuits vdd vss v dd pc0/?sc1 pc1/?sc? ?sc ci??uit pb0/xt1 pb1/xt? ?sc ci??uit see ?s?illato? se?tion see ?s?illato? se?tion an0~an7 sc?mn ssegm lcd panel pa0~pa7 pb0~pb6 pc0~pc6 pd0~pd3 0.1f
rev. 1.00 188 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 189 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be i mplemented wi thin 0.5 s a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be clr pcl or mov pcl, a. for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of several kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the accumulator . one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions such as inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.00 188 ??to?e? 01? ?01? rev. 1.00 189 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or t o a su broutine usi ng t he cal l i nstruction. t hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been c arried out. t his i s done by pl acing a re turn i nstruction ret i n t he subrout ine whi ch wi ll cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the c ondition of a c ertain da ta m emory or i ndividual bi ts. de pending upon t he c onditions, t he program will continue with the next instruction or skip over it and jump to the following instruction. these i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers . this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. however , whe n worki ng wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the hal t instruction for power -down operations and instructions to control the operation of the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.00 190 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 191 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a ? [m] add data memo ? y to acc 1 z ? c ? ac ? ? v addm a ? [m] add acc to data memo ? y 1 note z ? c ? ac ? ? v add a ? x add immediate data to acc 1 z ? c ? ac ? ? v adc a ? [m] add data memo ? y to acc with ca ?? y 1 z ? c ? ac ? ? v adcm a ? [m] add acc to data memo ? y with ca ?? y 1 note z ? c ? ac ? ? v sub a ? x su ? t ? a ? t immediate data f ? om the acc 1 z ? c ? ac ? ? v sub a ? [m] su ? t ? a ? t data memo ? y f ? om acc 1 z ? c ? ac ? ? v subm a ? [m] su ? t ? a ? t data memo ? y f ? om acc with ? esult in data memo ? y 1 note z ? c ? ac ? ? v sbc a ? [m] su ? t ? a ? t data memo ? y f ? om acc with ca ?? y 1 z ? c ? ac ? ? v sbcm a ? [m] su ? t ? a ? t data memo ? y f ? om acc with ca ?? y ? ? esult in data memo ? y 1 note z ? c ? ac ? ? v daa [m] de ? imal adjust acc fo ? addition with ? esult in data memo ? y 1 note c logic operation and a ? [m] logi ? al and data memo ? y to acc 1 z ? r a ? [m] logi ? al ? r data memo ? y to acc 1 z x ? r a ? [m] logi ? al x ? r data memo ? y to acc 1 z andm a ? [m] logi ? al and acc to data memo ? y 1 note z ? rm a ? [m] logi ? al ? r acc to data memo ? y 1 note z x ? rm a ? [m] logi ? al x ? r acc to data memo ? y 1 note z and a ? x logi ? al and immediate data to acc 1 z ? r a ? x logi ? al ? r immediate data to acc 1 z x ? r a ? x logi ? al x ? r immediate data to acc 1 z cpl [m] complement data memo ? y 1 note z cpla [m] complement data memo ? y with ? esult in acc 1 z increment & decrement inca [m] in ?? ement data memo ? y with ? esult in acc 1 z inc [m] in ?? ement data memo ? y 1 note z deca [m] de ?? ement data memo ? y with ? esult in acc 1 z dec [m] de ?? ement data memo ? y 1 note z rotate rra [m] rotate data memo ? y ? ight with ? esult in acc 1 none rr [m] rotate data memo ? y ? ight 1 note none rrca [m] rotate data memo ? y ? ight th ? ough ca ?? y with ? esult in acc 1 c rrc [m] rotate data memo ? y ? ight th ? ough ca ?? y 1 note c rla [m] rotate data memo ? y left with ? esult in acc 1 none rl [m] rotate data memo ? y left 1 note none rlca [m] rotate data memo ? y left th ? ough ca ?? y with ? esult in acc 1 c rlc [m] rotate data memo ? y left th ? ough ca ?? y 1 note c
rev. 1.00 190 ??to?e? 01? ?01? rev. 1.00 191 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom mnemonic description cycles flag affected data move m ? v a ? [m] move data memo ? y to acc 1 none m ? v [m] ? a move acc to data memo ? y 1 note none m ? v a ? x move immediate data to acc 1 none bit operation clr [m].i clea ? ? it of data memo ? y 1 note none set [m].i set ? it of data memo ? y 1 note none branch operation jmp add ? jump un ? onditionally ? none sz [m] skip if data memo ? y is ze ? o 1 note none sza [m] skip if data memo ? y is ze ? o with data movement to acc 1 note none sz [m].i skip if ? it i of data memo ? y is ze ? o 1 note none snz [m].i skip if ? it i of data memo ? y is not ze ? o 1 note none siz [m] skip if in ?? ement data memo ? y is ze ? o 1 note none sdz [m] skip if de ?? ement data memo ? y is ze ? o 1 note none siza [m] skip if in ?? ement data memo ? y is ze ? o with ? esult in acc 1 note none sdza [m] skip if de ?? ement data memo ? y is ze ? o with ? esult in acc 1 note none call add ? su ?? outine ? all ? none ret retu ? n f ? om su ?? outine ? none ret a ? x retu ? n f ? om su ?? outine and load immediate data to acc ? none reti retu ? n f ? om inte ?? upt ? none table read operation tabrd [m] read table (specifc page) to tblh and data memory ? note none tabrdc [m] read ta ? le ( ? u ?? ent page) to tblh and data memo ? y ? note none tabrdl [m] read ta ? le (last page) to tblh and data memo ? y ? note none miscellaneous n ? p no ope ? ation 1 none clr [m] clea ? data memo ? y 1 note none set [m] set data memo ? y 1 note none clr wdt clea ? wat ? hdog time ? 1 t ?? pdf clr wdt1 p ? e- ? lea ? wat ? hdog time ? 1 t ?? pdf clr wdt ? p ? e- ? lea ? wat ? hdog time ? 1 t ?? pdf swap [m] swap ni ?? les of data memo ? y 1 note none swapa [m] swap ni ?? les of data memo ? y with ? esult in acc 1 none halt ente ? powe ? down mode 1 t ?? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the t o and pdf flags may be af fected by the execution sta tus. t he t o a nd pdf fl ags a re c leared a fter bot h clr w dt1 a nd clr w dt2 instructions are consecutively executed. otherwise the t o and pdf fags remain unchanged.
rev. 1.00 19 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 193 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom instruction defnition adc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c adcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c add a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c add a,x add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c addm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c and a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z and a,x logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z andm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z
rev. 1.00 19? ??to?e? 01? ?01? rev. 1.00 193 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt1 pre-clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re a ll c leared. n ote t hat t his instruction w orks in conjunction w ith c lr w dt2 a nd m ust b e e xecuted al ternately w ith c lr w dt2 to h ave effect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt2 w ill have no e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt2 pre-clear w atchdog t imer description the t o, p df f ags and t he w dt are all cleared. n ote t hat t his i nstruction w orks i n conjunction with c lr w dt1 a nd m ust b e e xecuted al ternately w ith c lr w dt1 to h ave e ffect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt1 w ill h ave n o e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z
rev. 1.00 19 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 195 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z
rev. 1.00 19? ??to?e? 01? ?01? rev. 1.00 195 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none
rev. 1.00 196 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 197 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none
rev. 1.00 196 ??to?e? 01? ?01? rev. 1.00 197 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none
rev. 1.00 198 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 199 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none snz [m].i skip i f b it i of d ata m emory i s n ot 0 description if b it i o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c
rev. 1.00 198 ??to?e? 01? ?01? rev. 1.00 199 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none
rev. 1.00 ? 00 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 ?01 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom tabrd [m] read ta ble ( specifc p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( specifc p age) a ddressed b y t he t able p ointer p air (tbhp a nd t blp) i s mo ved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdc [m] read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( tblp) is moved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z
rev. 1.00 ?00 ??to?e? 01? ?01? rev. 1.00 ? 01 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package information. additional supplementary information with regard to pa ckaging is listed below. click on the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product t ape and reel specifcations) ? packing meterials information ? carton information
rev. 1.00 ? 0 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 ?03 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom 20-pin sop (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ? 06 bsc b 0. ? 95 bsc c 0.01 ? 0.0 ? 0 c 0.50 ? bsc d 0.10 ? e 0.050 bsc f 0.00 ? 0.01 ? g 0.016 0.050 h 0.008 0.013 0 8 symbol dimensions in mm min. nom. max. a 10.30 bsc b 7.5 bsc c 0.31 0.51 c 1 ? .8 bsc d ? .65 e 1. ? 7 bsc f 0.10 0.30 g 0. ? 0 1. ? 7 h 0. ? 0 0.33 0 8
rev. 1.00 ?0? ??to?e? 01? ?01? rev. 1.00 ? 03 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom 20-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ? 36 bsc b 0.15 ? bsc c 0.008 0.01 ? c 0.3 ? 1 bsc d 0.069 e 0.0 ? 5 bsc f 0.00 ? 0.010 g 0.016 0.050 h 0.00 ? 0.010 0 8 symbol dimensions in mm min. nom. max. a 6.0 bsc b 3.9 bsc c 0. ? 0 0.30 c 8.66 bsc d 1.75 e 0.635 bsc f 0.10 0. ? 5 g 0. ? 1 1. ? 7 h 0.10 0. ? 5 0 8
rev. 1.00 ? 0 ? ?? to ? e ? 01 ? ? 01 ? rev. 1.00 ?05 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom 24-pin sop (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ? 06 bsc b 0. ? 95 bsc c 0.01 ? 0.0 ? 0 c 0.606 bsc d 0.10 ? e 0.050 bsc f 0.00 ? 0.01 ? g 0.016 0.050 h 0.008 0.013 0 8 symbol dimensions in mm min. nom. max. a 10.30 bsc b 7.5 bsc c 0.31 0.51 c 15. ? bsc d ? .65 e 1. ? 7 bsc f 0.10 0.30 g 0. ? 0 1. ? 7 h 0. ? 0 0.33 0 8
rev. 1.00 ?0? ??to?e? 01? ?01? rev. 1.00 ? 05 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom 24-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ? 36 bsc b 0.15 ? bsc c 0.008 0.01 ? c 0.3 ? 1 bsc d 0.069 e 0.0 ? 5 bsc f 0.00 ? 0.010 g 0.016 0.050 h 0.00 ? 0.010 0 8 symbol dimensions in mm min. nom. max. a 6.0 bsc b 3.9 bsc c 0. ? 0 0.30 c 8.66 bsc d 1.75 e 0.635 bsc f 0.10 0. ? 5 g 0. ? 1 1. ? 7 h 0.10 0. ? 5 0 8
rev. 1.00 ? 06 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 ?07 ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom 28-pin sop (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ? 06 bsc b 0. ? 95 bsc c 0.01 ? 0.0 ? 0 c 0.705 bsc d 0.10 ? e 0.050 bsc f 0.00 ? 0.01 ? g 0.016 0.050 h 0.008 0.013 0 8 symbol dimensions in mm min. nom. max. a 10.30 bsc b 7.50 bsc c 0.31 0.51 c 17.9 bsc d ? .65 e 1. ? 7 bsc f 0.10 0.30 g 0. ? 0 1. ? 7 h 0. ? 0 0.33 0 8
rev. 1.00 ?06 ??to?e? 01? ?01? rev. 1.00 ? 07 ?? to ? e ? 01 ? ? 01 ? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom 28-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ? 36 bsc b 0.15 ? bsc c 0.008 0.01 ? c 0.390 bsc d 0.069 e 0.0 ? 5 bsc f 0.00 ? 0.010 g 0.016 0.050 h 0.00 ? 0.010 0 8 symbol dimensions in mm min. nom. max. a 6.0 bsc b 3.9 bsc c 0. ? 0 0.30 c 9.9 bsc d 1.75 e 0.635 bsc f 0.10 0. ? 5 g 0. ? 1 1. ? 7 h 0.10 0. ? 5 0 8
rev. 1.00 ? 08 ?? to ? e ? 01 ? ? 01 ? rev. 1.00 pb ??to?e? 01? ?01? HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom HT66F0175/ht66f0185 a/d 8-bit flash mcu with eeprom copy ? ight ? ? 01 ? ? y h ? ltek semic ? nduct ? r inc. the info ? mation appea ? ing in this data sheet is ? elieved to ? e a ?? u ? ate at the time of pu ? li ? ation. howeve ?? holtek assumes no ? esponsi ? ility a ? ising f ? om the use of the specifcations described. the applications mentioned herein are used solely fo ? the pu ? pose of illust ? ation and holtek makes no wa ?? anty o ? ? ep ? esentation that su ? h appli ? ations will ? e suita ? le without fu ? the ? modifi ? ation ? no ? ? e ? ommends the use of its p ? odu ? ts fo ? appli ? ation that may p ? esent a ? isk to human life due to malfun ? tion o ? othe ? wise. holtek's p ? odu ? ts a ? e not autho ? ized fo ? use as ?? iti ? al ? omponents in life suppo ? t devi ? es o ? systems. holtek ? ese ? ves the ? ight to alte ? its products without prior notifcation. for the most up-to-date information, please visit ou ? we ? site at http://www.holtek. ? om.tw.

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